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Hello community!
I'm new here and have no prior experience with Cypress products. We are working on a solution to stream mpeg2-ts from a file over usb to an ASIC (proprietary stream manipulation which we have no control on) and then back over usb to another file.
MPEG_TS (Linux PC) --> USB --> 8bit parallel into ASIC --> 8bit parallel out from ASIC --> USB --> MPEG_TS
This is probably trivial for someone with experience with FX2LP or similar. For me however there are a lot of unknowns and a not so smooth learning curve. I'm looking for advice to get started faster, and to avoid usual pitfalls. I found that most of the AppNotes are geared towards getting the stream into the PC. I could not find any that explicitly talk about putting it out to parallel. All help is welcome!
regards
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Hello,
As per my understanding, you would like toggle the SOP line on your ASIC based on data match in the packet header. You could use a GPIO from ports A,C or E to do the same. If you would like to assert the line after every 188 byte packet, you could also set the FLAGx pins to be asserted after 188 bytes are received. Please let me know if this answers your question?
Best Regards,
Sananya
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Hello,
You could use the slave FIFO interface (configured as 8 bit data bus) in FX2LP for streaming data in and out from ASIC. We have an example project for stream IN MPEG2-TS data as you mentioned in the App Note FX2LP TV Dongle Reference Design.
You can however modify this project with the help of the App Note FX2LP GPIF and Slave FIFO examples which configures one FX2LP to send data out on its slave FIFO interface as well.
Please let us know if you have any issues with the firmware.
Best Regards,
Sananya
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Thanks Sananya! I have been working with the examples you've pointed to, things are getting clearer now. Though there is one issue that I haven't been able to figure out. As you would know, in the mpeg stream each 188 byte packet starts with 0x47. At the start of the stream the ASIC expects the SOP line to be asserted, is there a simple way to do this? Maybe something like an interrupt on match or toggle a control line on data match?
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Hello,
As per my understanding, you would like toggle the SOP line on your ASIC based on data match in the packet header. You could use a GPIO from ports A,C or E to do the same. If you would like to assert the line after every 188 byte packet, you could also set the FLAGx pins to be asserted after 188 bytes are received. Please let me know if this answers your question?
Best Regards,
Sananya