I'm trying to establish a synchronous Slave FIFO read between the FX2 and an FPGA.
The FPGA is providing the interface clock (20MHz) and runs a state machine that toggles the SLRD and SLOE lines according to figure 9-17 in the Technical Reference Manual.
If I now send data over USB to EP2 I expect the data to be driven out on the FD (byte wide) lines. I get the right amount of rising clock edges according to how many bytes I have sent to EP2 until the empty flags gets deasserted. However, the FD lines seem to be stuck on the first byte, or are alternating between the first two bytes for the whole transmission. I attached a picture of the logic analyzer software.
Has anyone seen something like this before? Any solutions.
By any chance, can D0 and D7 give the same pattern? Did you confirm that they are not same as what is shown in the logic analyser?
If you have confirmed, please create a Tech Support Case.
I have met almost the same question except I'm using the internal clk. could you let me know if you have solve that problem. How to solve it?