FIFO Slave / GPIF interface clock direction

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cross mob
ChRO_4339966
Level 3
Level 3

Hello,

I am considering using FX3 as a bridge between USB and FPGA.

It would be mainly used to pass data from USB to application via FX3 at maximum BW (low traffic in other direction).

My project is at board design level.

Looking at documentation and tools, it looks like 32-bit synchronous FIFO Slavemode  @ 100 MHz would be OK for me.

All implementations I found describe an interface where FPGA is master of the clock.

I would like to keep the ability to have FX3 driving this clock (still using maximum frequency, ie 100 MHz).

Example design provided in GPIF designer does not allow to modify clock direction.

Is there a simple solution to do so ? Or should I redesign everything (GPIF interface definition, state machine, FX3 firmware...)

Are there side effects using such a configuration ?

Thanks for your help

Christophe

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1 Solution
NoriTan
Employee
Employee
25 sign-ins 5 questions asked 10 sign-ins

In the GPIF II Designer application, create a new slave_fifo interface and then use the menu item "Save Project As Editable..." to save the project with a different file name.

GS004288.png

Now you can edit all parameters and the state machine is preserved.

GS004289.png

GS004290.png

Regards,

Noriaki

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2 Replies
NoriTan
Employee
Employee
25 sign-ins 5 questions asked 10 sign-ins

In the GPIF II Designer application, create a new slave_fifo interface and then use the menu item "Save Project As Editable..." to save the project with a different file name.

GS004288.png

Now you can edit all parameters and the state machine is preserved.

GS004289.png

GS004290.png

Regards,

Noriaki

Hello Noriaki,

Great, this worked for me.

I guess I'll be able to define CLK frequency through register setting/define in C code.

Thanks

Christophe

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