68013 works as a slavefifo with ep6 = bulk endpoint 512*2B buffer in a autoin mode;
fpga send data to 68013 with a 16bit self-increment data(0x0000-0xffff)@5MHz ifclk,but the 'slwr' and the 'fdata[15-0]' bus are only active during the cnt register is from 0-63,when cnt is 64-311 ,slwr<='1'; the cnt register trigers each clk_5M edge.so the data rate is actually 2MB/s.
the problem is that when we use the VC software we build with the cyapi(begin, wait, finish in a thread) to write the data into a txt file,we found that there would be some repeated data error as u can see in the attach file(2.txt). the err mostly appear when the last data is 0x3FFF, and the next one should be 0x4000,but always appear to be 0x8000,but after 512 0x80xx, it appears to turn back to 0x4100, so i believe that the fpga send the data correctly, but the slave fifo or the SIE may have some proble. (btw: if ifpga send data in 0-15 and when 16-311slwr<='1' then no error occurred, means if low the data rate to 0.5MB/s the system works well)
we believe that this is far from the max rate about 40MB/s talked in other thread. we also tested our board with the Cystreamer and got a perfect 35MB/s rate. we wonder why we meet such a problem. thx a lot!
the firmware and the fpga vhdl file are in the attachments
why i can't post attachments?
You may need to zip your files and upload (zip file).