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USB Low-Full-High Speed Peripherals

New Contributor II

Dear,

     I'm following this link: Interfacing FX2LP™ with Image Sensor – KBA95736

    The firmware is exactly the same,  image sensor and the connection wires are the same;

    (1) with my custom board and cy7c68013A-128AXC, the results are perfect,

    (2) but when I change to another cy7c68013a-56PAXC, as below (the schematic is given as attached.), I can get nothing. why?????

    image.jpg

    for the failed case, the oscilloscope shows that the signals are OK, and when I use a intermediate FPGA to check the signals, the data are also OK, as below,

Signal_is_OK_but_streamer_get_nothing.png

I really don't know what happened, why this test board cannot get any data from the image sensor ? do I need to do any extra setting for this board?

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1 Solution
Moderator
Moderator

Hello,

If you are using the exact firmware from this KBA: Interfacing FX2LP™ with Image Sensor – KBA95736 , it uses FX2LP in slave FIFO mode where the data is accepted IN when the SLWR line is low (LV as per your traces).

We see that the data is sent when the LV is high from the FIFO master (sensor/FPGA) which should not be the case.

Also, as per the flow chart mentioned in the KBA. The data is committed to the host when FV (VSYNC) is high.

What is the observation from the host side? Do you see a black image?

Please share your custom board schematic.

Thanks,

Yatheesh

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3 Replies
Moderator
Moderator

Hello,

If you are using the exact firmware from this KBA: Interfacing FX2LP™ with Image Sensor – KBA95736 , it uses FX2LP in slave FIFO mode where the data is accepted IN when the SLWR line is low (LV as per your traces).

We see that the data is sent when the LV is high from the FIFO master (sensor/FPGA) which should not be the case.

Also, as per the flow chart mentioned in the KBA. The data is committed to the host when FV (VSYNC) is high.

What is the observation from the host side? Do you see a black image?

Please share your custom board schematic.

Thanks,

Yatheesh

View solution in original post

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New Contributor II

Dear Yatheesh,

     Great thanks for your quick response. the problem seems very strange, how can I get the image from this simple little board?

     The previous one with 128Pin has no intermediate FPGA, the results are perfect (I stopped testing it yesterday).

     Sorry that the SLWR you mentioned, I've playing this for 2 days, forgot having changed it (FIFOPINPOLAR). 

   

     I'm now testing a new design, this time it is also a cy7c68013-56P, + intermediate Spartan FPGA + MT9M001/OV7725, I got the image with this custom one too. Schematics are given as below (I have to cut image one by one, I don't know why I cannot upload pdf files here?),

     001.png

002.png

   003.png

004.png

     To make a comparison with the above one, this time I didn't change even a single byte, and use the firmware to test my little board, still not successful. the code is given as below (sorry I don't find any place to upload my project, thus paste the main codes here);

     here I use the frame_init function to add 5 bytes to each frame start position.  the interrupt for each frame is.

     void ISR_EXTR0(void) interrupt  0 //using 0

     {

           vendorCmdIssued = TRUE;   // added bymc

      }

   

      I can get the 5 byte header (you can see I got success packets 448),  still no image data, the streaming works as below (you can see that the transfer rate keeps at 0)

005.png

if I comment out the frame_init()  function, the results would be as below,

006.png

#include "fx2.h"

#include "fx2regs.h"

#include "syncdly.h"            // SYNCDELAY macro

#include "USB_Camera_Demo.h" // for usbcam specific IO definitions

extern BOOL GotSUD;             // Received setup data flag

extern BOOL Sleep;

extern BOOL Rwuen;

extern BOOL Selfpwr;

//-----------------------------------------------------------------------------

// Constants

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Global Variables

//-----------------------------------------------------------------------------

BYTE Configuration;             // Current configuration

BYTE AlternateSetting;          // Alternate settings

WORD packetSize;

extern unsigned char frame_flag;

BOOL vendorCmdIssued=FALSE;

//-----------------------------------------------------------------------------

// Task Dispatcher hooks

//   The following hooks are called by the task dispatcher.

//-----------------------------------------------------------------------------

void TD_Init(void)              // Called once at startup

{

// set the CPU clock to 48MHz, Default 12MHz(Page 333)

//CPUCS = 0x02;  //12MHZ CLKOUT ENALBE 

  //CPUCS = 0x0a;  //24MHZ CLKOUT ENALBE

  CPUCS = 0x12;  //48MHZ CLKOUT ENALBE

SYNCDELAY;

//Interface Configure(Page 334)

IFCONFIG =0x03; //Ñ¡ÔñΪÍⲿʱÖÓ£¬ÇÒΪͬ²½slaveFIFOģʽ,ÊäÈëIFCLK(5~48MHz)(0000_0011)

//IFCONFIG =0x0B;//Ñ¡ÔñΪÍⲿʱÖÓ£¬ÇÒΪÒì²½slaveFIFOģʽ,²»ÐèÒªIFCLK

SYNCDELAY;

//Configure REVCTL for Chip Revision Control(Page 344)

REVCTL = 0x03; //Cypress highly recommends setting both bits to 1

SYNCDELAY;

Rwuen = TRUE; // Enable remote-wakeup

//--------------------------------------------------------

EP1OUTCFG = 0xA0; // default values(Page 346)

SYNCDELAY;        

EP1INCFG = 0xA0;  // default values(Page 346)

SYNCDELAY;        

EP2CFG = 0xE0; // enabled, quad buffered, 512B, IN, bulk fifo, 4 buffer(Page 347)

// EP2CFG = 0xE8; // enabled, quad buffered, 1024B, IN, bulk fifo£¬ 4 buffer

SYNCDELAY;       

EP4CFG = 0x60; // disabled...

SYNCDELAY;       

EP6CFG = 0x60; // disabled...

SYNCDELAY;        

EP8CFG = 0x60; // disabled...

SYNCDELAY;

//--------------------------------------------------------

//Configure the EPxFIFOCFG(Page 349)

EP2FIFOCFG = 0x08; // autoin, 8 Bit Wide

// EP2FIFOCFG = 0x09; // autoin, 16 Bit Wide

SYNCDELAY;       

EP4FIFOCFG = 0x00; // no-autoOUT, bytewide

SYNCDELAY;                   

EP6FIFOCFG = 0x00; // no-autoOUT, bytewide

SYNCDELAY;                   

EP8FIFOCFG = 0x00; // no-autoOUT, bytewide

SYNCDELAY;  

//--------------------------------------------------------

//Configure PIN Polarity

PORTACFG |= 0x40; //IFCOG[1:0] = 11(Slave FIFO Mode), Set PORTACFG[6] to USE PA7-SLCS (Page 375)

SYNCDELAY;

FIFOPINPOLAR = 0x07; //Set SLWR High Valid; PKTEND£¬SLOE£¬SLRD Low Active(Page 342)

SYNCDELAY;

//--------------------------------------------------------

SYNCDELAY;

  EP2AUTOINLENH = 0x02; // EZ-USB automatically commits data in 512-byte chunks

// EP2AUTOINLENH = 0x04; // EZ-USB automatically commits data in 1024-byte chunks

SYNCDELAY;

  EP2AUTOINLENL = 0x00;

SYNCDELAY;

//Set Autopointer, enable dual autopointer(Page 328)

AUTOPTRSETUP |= 0x01;

//FLAGA - User-Programmable Level; FLAGB - FIFO Full, FLAGC - FIFO Empty: (L: Valid)(Page 338)

PINFLAGSAB = 0x00;//0x8a;

SYNCDELAY;

PINFLAGSCD = 0x00;//0x08;

SYNCDELAY;           

SYNCDELAY;

FIFORESET = 0x80;// activate NAK-ALL to avoid race conditions

SYNCDELAY;

FIFORESET = 0x02;// reset, FIFO 2

SYNCDELAY;

  FIFORESET = 0x04;// reset, FIFO 4

SYNCDELAY;

FIFORESET = 0x06;// reset, FIFO 6

SYNCDELAY;

  FIFORESET = 0x08;// reset, FIFO 8

SYNCDELAY;

FIFORESET = 0x00;// deactivate NAK-AL

SYNCDELAY;

//------------------------------------------------------------

//Configure Start Trigger

OED |= (1<<5); //PD5 0:Input; 1:output

PD5 = 0;

//Configure INT0

OEA &= ~(1<<0); //PA0-INT0 0:Input

PORTACFG |= (1<<0); //Configure PA0 as INT0#

IT0 = 1; //When ITx = 1, posedge edge Sample; When ITx = 0, low-level Sample.

IE |= (1<<0); //Enable INT0

}

void frame_init(void){

if( !( EP24FIFOFLGS & 0x02 ) )

{

    // EP2EF=0 when FIFO is not  empty, host sent pkt.

    OUTPKTEND = 0x82;  // SKIP=1, do NOT pass buffer on to master

}

EP2FIFOBUF[0]=0xFF;    //5bytes of Header used by the Preview Utility to detect the Start of Transmission

EP2FIFOBUF[1]=0xFF;

EP2FIFOBUF[2]=0xFF;

EP2FIFOBUF[3]=0xFF;

EP2FIFOBUF[4]=0xFF;

SYNCDELAY;

EP2BCH = 0x00;

SYNCDELAY;

EP2BCL = 0x05; // pass newly-sourced buffer on to host

SYNCDELAY;

}

void TD_Poll(void)              // Called repeatedly while the device is idle

{

if(vendorCmdIssued)     // if Vendor command issued

  {

      frame_init();    // pop out the last buffer that is NOT 16384Bytes

  vendorCmdIssued=FALSE;

}

return;  // noting need here for we are using AUTOIN mode

}

BOOL TD_Suspend(void)          // Called before the device goes into suspend mode

{

   return(TRUE);

}

BOOL TD_Resume(void)          // Called after the device resumes

{

   return(TRUE);

}

//-----------------------------------------------------------------------------

// Device Request hooks

//   The following hooks are called by the end point 0 device request parser.

//-----------------------------------------------------------------------------

BOOL DR_GetDescriptor(void)

{

   return(TRUE);

}

BOOL DR_SetConfiguration(void)   // Called when a Set Configuration command is received

{

   Configuration = SETUPDAT[2];

   return(TRUE);            // Handled by user code

}

BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received

{

   EP0BUF[0] = Configuration;

   EP0BCH = 0;

   EP0BCL = 1;

   return(TRUE);            // Handled by user code

}

BOOL DR_SetInterface(void)  // Called when a Set Interface command is received

{

   AlternateSetting = SETUPDAT[2];

   return(TRUE);            // Handled by user code

}

BOOL DR_GetInterface(void)      // Called when a Set Interface command is received

{

   EP0BUF[0] = AlternateSetting;

   EP0BCH = 0;

   EP0BCL = 1;

   return(TRUE);            // Handled by user code

}

BOOL DR_GetStatus(void)

{

   return(TRUE);

}

BOOL DR_ClearFeature(void)

{

   return(TRUE);

}

BOOL DR_SetFeature(void)

{

   return(TRUE);

}

BOOL DR_VendorCmnd(void)

{

   return(TRUE);

}

//----------------------------------------------------------------------------

// USB Interrupt Handlers

//   The following functions are called by the USB interrupt jump table.

//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler

void ISR_Sudav(void) interrupt 0

{

   // enable the automatic length feature of the Setup Data Autopointer

   // in case a previous transfer disbaled it

   SUDPTRCTL |= bmSDPAUTO;

   GotSUD = TRUE;            // Set flag

   EZUSB_IRQ_CLEAR();

   USBIRQ = bmSUDAV;         // Clear SUDAV IRQ

}

// Setup Token Interrupt Handler

void ISR_Sutok(void) interrupt 0

{

   EZUSB_IRQ_CLEAR();

   USBIRQ = bmSUTOK;         // Clear SUTOK IRQ

}

void ISR_Sof(void) interrupt 0

{

   EZUSB_IRQ_CLEAR();

   USBIRQ = bmSOF;            // Clear SOF IRQ

}

void ISR_Ures(void) interrupt 0

{

   if (EZUSB_HIGHSPEED())

   {

      pConfigDscr = pHighSpeedConfigDscr;

      pOtherConfigDscr = pFullSpeedConfigDscr;

      packetSize = 512;

   }

   else

   {

      pConfigDscr = pFullSpeedConfigDscr;

      pOtherConfigDscr = pHighSpeedConfigDscr;

      packetSize = 64;

   }

 

   EZUSB_IRQ_CLEAR();

   USBIRQ = bmURES;         // Clear URES IRQ

}

void ISR_Susp(void) interrupt 0

{

   Sleep = TRUE;

   EZUSB_IRQ_CLEAR();

   USBIRQ = bmSUSP;

}

void ISR_Highspeed(void) interrupt 0

{

   if (EZUSB_HIGHSPEED())

   {

      pConfigDscr = pHighSpeedConfigDscr;

      pOtherConfigDscr = pFullSpeedConfigDscr;

      packetSize = 512;

   }

   else

   {

      pConfigDscr = pFullSpeedConfigDscr;

      pOtherConfigDscr = pHighSpeedConfigDscr;

      packetSize = 64;

   }

   EZUSB_IRQ_CLEAR();

   USBIRQ = bmHSGRANT;

}

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New Contributor II

Dear Yatheesh,

     I got the signals finally, the post can be closed now. It is all my fault, the intermediate board between the image ensor and the little board has a faulty connection.

Anyway, Great thanks

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