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USB Low-Full-High Speed Peripherals

New Contributor

Hello, dear

TS Data -> CY7c68013->PC

recently,i am doing a job which mpeg2-Ts stream Transferred to a computer.i used cy7c68013a-56 chip,endpoint2 bulk in 4xbuffer.Frimware,i reference to http://www.cypress.com/?rID=39714

My problem,

in most case, FIFO buffer is filled with zero (0x00,0x00,0x00....) instead of real ts data.

1 out of 100 test case,  FIFO buffer is filled with valid packet (0x47,....).

Here's what I tried so far.

I tried both Free Running MPEG CLK & Gated MPEG CLK but it has same problem.

SLRD#/SLOE#/ PKTEND  ->Pulled High

SLCS#/FIFOADR [0]/FIFOADR [1] -> Pulled Low

I tried PKTEND Pulled Low

tried window application on sync mode & async mode, but same problem. (xferData, beginXferData)

tried cypress streamer tool -> it has same symptom (mostly zero packet, randomly valid packet). tried with fx2 & fx3 window application. same problem.

here's my firmware code. could you pls suggest where to check, or fix?

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

CPUCS = 0x10;

SYNCDELAY;

#ifdef _USE_INTERNAL_IF

IFCONFIG = 0xCB; // use IFCLK pin driven by external logic (5MHz to 48MHz)  Inverted  : 0x13 Async

#else

IFCONFIG = 0x03; // use IFCLK pin driven by internal logic (5MHz to 48MHz) sync

#endif

EP2CFG = 0xE0; // EP2 is DIR=IN, TYPE=BULK,SIZE=512,BUF x4 
SYNCDELAY;
EP4CFG = 0x00; // clear valid bit
SYNCDELAY; //
EP6CFG = 0x00;  // clear valid bit
SYNCDELAY; //
EP8CFG = 0x00; // clear valid bit
SYNCDELAY;

// Clear out any committed packets
    FIFORESET = 0x80; //activate NAK-ALL to avoid race conditions
    SYNCDELAY;
    FIFORESET = 0x82;
    SYNCDELAY;
    FIFORESET = 0x84;
    SYNCDELAY;
    FIFORESET = 0x86;
    SYNCDELAY;
    FIFORESET = 0x88;
    SYNCDELAY;
    FIFORESET = 0x00;  //deactivate NAK-ALL
    SYNCDELAY;

EP2FIFOCFG = 0x08; // EP2 is INFM = 0, AUTOOUT=0, AUTOIN=1, ZEROLEN=0, WORDWIDE=0  0x0C : Auto In = 1 , ZeroLen = 1
SYNCDELAY;

FIFOPINPOLAR = 0x04; // set all slave FIFO interface pins as active low, 0x04 active hi  need to check...
SYNCDELAY;
EP2AUTOINLENH = 0x02; // EZ-USB automatically commits data in 512-byte chunks
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;

PORTACFG = 0x00;  // used PA7/FLAGD as a port pin, not as a FIFO flag  #SLCS = 0x80
SYNCDELAY;

PINFLAGSAB = 0x00;  // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY;    // FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD = 0x00;  // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
SYNCDELAY;     // won't generally need FLAGD

EP2FIFOPFH = 0x80; // you can define the programmable flag (FLAGA)
SYNCDELAY; // to be active at the level you wish
EP2FIFOPFL = 0x00;
SYNCDELAY;

REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1  by TRM Doc 9.3.9 Auto In/Out
SYNCDELAY;

IOA = 0; //

// enable dual autopointer feature
//AUTOPTRSETUP |= 0x01;

EP0BCH = 0;
EP0BCL = 64;

// We want to get SOF interrupts
USBIE |= bmSOF;

  Rwuen = TRUE;

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

I'm looking forward answer.

Thanks.

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1 Solution
Moderator
Moderator

Hello,

1. Please try the application note firmware as it is on the FX2LP device by defining the required directive FREE or GATED in the firmware.

2. Probe the data lines and the SLWR/MPEG_Valid line using a logic analyzer, and check if the data (non zero) is being sent at every assert (high) of MPEG_Valid line. please share the logs.

Let me know if it works.

If you are receiving zero packets even after checking the above two points, please send the schematic.

Thanks,

Yatheesh

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5 Replies
Moderator
Moderator

Hello,

1. Please try the application note firmware as it is on the FX2LP device by defining the required directive FREE or GATED in the firmware.

2. Probe the data lines and the SLWR/MPEG_Valid line using a logic analyzer, and check if the data (non zero) is being sent at every assert (high) of MPEG_Valid line. please share the logs.

Let me know if it works.

If you are receiving zero packets even after checking the above two points, please send the schematic.

Thanks,

Yatheesh

View solution in original post

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New Contributor

Dear Yatheesh,

Thank you for your quick reply.

1) FREE or GATED directive

I can't find FREE or GATED directive on my directory (cypress\CY3684_EZ-USB_FX2LP_DVK\1.1\Firmware\)

where can I find "application note firmware" source code you mentioned?

As far as i know difference between "FREE" and "GATED" IS "IFCONFIG" value.

IFCONFIG=:0xCB (GATED) , : 0x03 (FREE)

2) I don't have logic analyzer, so I'm trying to find a way if I can rent. Is it possible to check schematic before I rent? I attached schematic.

Thank you.

Best Regards.

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Moderator
Moderator

Hello,

The source code is present in the zip folder present in the AN58069 Application note page: https://www.cypress.com/documentation/application-notes-obsolete/an58069-implementing-8-bit-parallel...

Please download the zip folder in the page for obtaining the firmware.

Thanks,

Yatheesh

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New Contributor

Dear Yatheesh,

I both tried 2 mode but it has same symptom.

Have you check our schematic ?

Thanks.

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Moderator
Moderator

Hello,

I have checked the interface connections on the FX2LP side in the schematic. They seem fine.

Please confirm if the data is being sent from the master using any logic analyzer, this will give a clear understanding of the issue.

Also, in the application note MPEG_Valid signal is active high, please confirm the same from the datasheet of the master. 

Thanks,

Yatheesh

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