We have been performing some tests under Linux with the CY7C65215A running in i2c master mode.
When no receiver is present with the transmitted address or the receiving device is busy and unable to respond so a NACK occurs that the CY7C65215A appears to be holding the SCL line low until a USB timeout occurs.
Would you please advise how to overcome this issue? We are running under Linux.
The issue usually occurs when the slave and master are out of sync.
The solution is to temporarily set the IOs back to GPIO, then manually clock SDA until it is released.
Why would the master go out of sync when a NACK occurs? This is a standard i2c event... I'd have expected the master to release its SCL not hold it low.
How can the i2c master IO be changed to GPIO? I thought the function of the i2c master on the CY7C65215A was fixed?
Apologies for the delay in response.
Can you please probe both the SDA and SCL lines and share the traces?