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USB Low-Full-High Speed Peripherals

YoIs_1298666
Contributor II

Hello,

I have three questions about CY7C65213A/CY7C65213A configured for Self-Powered.

1. Is the TXD pin (1 pin) IOL-VOL specification  the GPIO DC specification?

YoIs_1298666_0-1617759662295.png

2. Is there any problem with VCCIO: OFF and VCC: ON in the figure below?

 Or does VCCIO have to be turned on before VCC?

YoIs_1298666_1-1617759953881.png

3. Is RESET connected to VBUS (VCC) via a resistor to remove the following USBDP 1.5k pull-up resistor?

YoIs_1298666_2-1617760330378.png

YoIs_1298666_3-1617760368738.png

Best regards,

Yocchi

 

 

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1 Solution
MallikaK_22
Moderator
Moderator

Hello,

1. The DC specifications of the GPIO also applies to the TXD pin.

2. There is no power supply sequence as such for the chip. However, please note that VCCIO is used for IO and the core. If you do not power up the IO and the core, the chip wouldn't work. Nonetheless, this configuration won't damage the chip.

3. RESET is connected to VBUS using resistor divider to ensure the pull up on D+ line is not present when VBUS isn't supplied.

Regards,

Mallika

Mallika

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4 Replies
MallikaK_22
Moderator
Moderator

Hello,

1. The DC specifications of the GPIO also applies to the TXD pin.

2. There is no power supply sequence as such for the chip. However, please note that VCCIO is used for IO and the core. If you do not power up the IO and the core, the chip wouldn't work. Nonetheless, this configuration won't damage the chip.

3. RESET is connected to VBUS using resistor divider to ensure the pull up on D+ line is not present when VBUS isn't supplied.

Regards,

Mallika

Mallika

View solution in original post

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YoIs_1298666
Contributor II

Hello Mallika-san,

 

Thank you very much for your reply.

It  can run well in both conditions, right?

YoIs_1298666_0-1617781092898.png

And, is Power-on reset released at the rising edge of VCCIO, and Brown-out reset also resetting at the falling edge of VCCIO?

Best regards,

Yocchi

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MallikaK_22
Moderator
Moderator

Hello Yocchi,

>> Ideally, there is no power up sequence of VCC and VCCIO. Very small delays in the order of nanoseconds (ns) do not matter. Powering up both the VCC and VCCIO together will work fine. It is also possible to have VCCIO present and connect VBUS later.

>> The POR mechanism depends upon power mode- i.e. how the RESET pin is connected, to VBUS or VCCIO. In the datasheet ( the application diagram pointed out by you previously), for Self Powered configuration RESET is tied to VBUS, after power-on when VCCIO is present it will cause POR. 

Regards,

Mallika

Mallika
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YoIs_1298666
Contributor II

Hello Mallika-san,

 

Thank you very much.

 

Best regards,

Yocchi

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