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USB Low-Full-High Speed Peripherals

Contributor II

We are currently using  CY7C64315-16LKXIT

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We are working on programming these chips through a microcontroller, instead of using a programmer header as done on previous projects using this part. We have run into a couple of issues and would like to pass on some questions to Cypress.

1. What is the best protocol for programming the CY7C64315 device with a microcontroller? Right now we are working on programming them with the ISSP protocol, going off information found in AN44168
2. Is there a version of the ISSP source code that explicitly supports CY7C64315?
3. If not, what are the parameters/vectors needed by CY7C64315 that needs to be set in the HSSP_CY8Cxxxx source code? We see some information for CY7C64215, how compatible is this with CY7C64315?

  • What is SECURITY_BYTES_PER_BANK?
  • Which of the 3 existing CHECKSUM_SETUP values apply to CY7C64315 or does it require a new one? (Existing values are: CHECKSUM_SETUP_21_23_27_TST110_TMG110, CHECKSUM_SETUP_22_24_28_29_TST120_TMG120_TMA120, CHECKSUM_SETUP_24_24A)
  • Which of the 2 existing PROGRM_BLOCK values applies to the 64315, or does it require a new one? (Existing values are: PROGRAM_BLOCK_21_22_23_24_28_29_TST_TMG_TMA, PROGRAM_BLOCK_27)
  • ?Is MULTI_BANK the same as (NUM_BANKS > 1)
  • What is the target_id_v[] setting for CY7C64315?

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1 Solution
Moderator
Moderator

Hi,

Please find the attached project. This supports HSSP for CY7C64315. AN59389 was modified to support HSSP for enCore V devices.

Following are a few points to note about the project:

1. The project writes 0xB9 to the entire flash and sets flash security to "U" for all blocks.

2. Table below shows the connections between Host and target

SIGNAL HOST TARGET

  ---------------------

  SDATA P1.2 P1.0

  SCLK  P1.3  P1.1

  XRES P0.0  XRES

  PWR  P0.1  Vdd

  TP      P0.7  n/a

3. Right now "powercycle" mode of programming is enabled. Uncomment the #define on line61 in issp_directives.h to use "Reset Mode".

4. The project is developed for CY8C29866-24AXI.

5. The LCD can be connected to Port2 to see the status of programming (displayed on line0) and read SiliconID(displayed on line1). Refer LCD user module datasheet for LCD connections.

6. Erase EncoreV flash using "PSoC Programmer software". Then program EncoreV using HSSP. Use PSoC Programmer to read EncoreV again to verify if the flash was actually written.

Regards,

Hemanth

Hemanth

View solution in original post

2 Replies
Moderator
Moderator

Hi,

Please find the attached project. This supports HSSP for CY7C64315. AN59389 was modified to support HSSP for enCore V devices.

Following are a few points to note about the project:

1. The project writes 0xB9 to the entire flash and sets flash security to "U" for all blocks.

2. Table below shows the connections between Host and target

SIGNAL HOST TARGET

  ---------------------

  SDATA P1.2 P1.0

  SCLK  P1.3  P1.1

  XRES P0.0  XRES

  PWR  P0.1  Vdd

  TP      P0.7  n/a

3. Right now "powercycle" mode of programming is enabled. Uncomment the #define on line61 in issp_directives.h to use "Reset Mode".

4. The project is developed for CY8C29866-24AXI.

5. The LCD can be connected to Port2 to see the status of programming (displayed on line0) and read SiliconID(displayed on line1). Refer LCD user module datasheet for LCD connections.

6. Erase EncoreV flash using "PSoC Programmer software". Then program EncoreV using HSSP. Use PSoC Programmer to read EncoreV again to verify if the flash was actually written.

Regards,

Hemanth

Hemanth

View solution in original post

Contributor II

Thank you Hemanth.

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