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USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

Hi all,

   

I'm using a CY7C68013a hi-speed USB interface chip.

   

According to the docs there are thee modes: Slave FIFO, GPIF Master, and Ports I/O

   

In Slave FIFO mode, the CTL/FLAG pins operate as FLAGA...FLAGC

   

In GPIF Mode, the pins operate as CTL0...CTL2 and are controlled by GPIFIDLECTL ( except when doing a transaction )

   

... My question is what these three pins do when in Ports I/O mode? - are they tri-state or under control of GPIFIDLECTL,... ?

   

Also - do writes to GPIFIDLECTL have immediate effect (on these pins)when in GPIF idle mode or is that sampled when entering idle mode?

   

- Thanks!

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1 Reply
Employee

Hi Nigel,

Please see the following URL: Utilization of the Unused GPIF Control Lines in Port Mode

Thank You & Regards,

Sudheer

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