4 endpoint in slave sync fifo 2 bit

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Anonymous
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hi 

   

I  have this code for 4 endpoint, but i cant send data from fpga to fx3.

   

I can send data by an endpoint to fx3 but with another endpoint I cant.

   

What is the problem?

   

Can the problem from verilog coding?

   

In this code i want have 4 endpoint and I want to send data with two channel to fx3. I changed the slavefifosync project.

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Anonymous
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I see that you are using thread 0 and thread 2 for P-port to USB channel. The flags will reflect the values of DMA buffer. First ensure that the buffer is available (if the host does not need the buffers data, then it wll get filled and will not be available any further). So, when the buffer is available to be written, then the ready flag will go low. Please make sure that the buffers are empty (hence ready to be written by the master). Also, notice the address lines the FPGA is selecting. I see that you have not used flags for USB-to-P-port communication. I recommend you to use current thread flags (instead of dedicated thread flags). To test, you can discard the buffer in the FX3 firmware if the host is not asking for the data. This way, we make sure that the buffers are available and we can validate the functionality of flags. Also, I recommend you to test once with the AN65974 exact firmware, which will give you the clarity of flag behaviour 

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