USB hosts hubs transceivers Forum Discussions
I reinstalled and repaired the SDK several times but the header file is not able to be resolved in the source code. This header file is not present in the workspace, it is an inbuilt include file. How can I solve the issue?
Thanking you.
Hi All,
We are working on NXP'S imx8 based custom design. we had interface cypress's CYUSB3304-68LTXI USB hub. It is working fine with SOC.
We need to change the drive strength of the USB HUB. So, we have following queries
1. Is it possible to change the drive strength of USB HUB after config in i2c slave mode?
2. If yes then please share the document for that.
3. Is it possible to configure in run time?
let me know if you need more information.
Reg,
Parth
Show LessHi, we are designing a new USB hub, and I have a question about the #PWR and #OVR pins. If our downstream devices are self powered, is there any problem with bypassing the #PWR and #OVR pins? I am planning to leave the #PWR pins floating and pulling the #OVR pins high with 10k resistors. Will there be any issues with enumeration if the downstream devices are powered up independently of the hub?
Thank you
Show LessHi,
I'd like to use CY7C65632/42 for the project.
I see there's LED control pins on CY7C65632/42 series
But I'm wondering -
1. What is the default control behaviour for GREEN/AMBER?
2. Can you control the LED behaviour?
3. How can you control, by pre-programmed into EEPROM? Or is it either one situation, once either choose EEPROM or LED function?
It's because we want to have LED indicator shows USB data transfer,
and I see there are LED control pins but I don't understand the description fully nor the exact LED control behaviour.
Could you kindly help to elaborate a bit more in detail?
Thanks,
Bertram
Show LessWe're having problems with a device which uses CYUSB3304 configured in I2C slave mode as a USB hub. When we send a call to the 7-bit address 0x60, the I2C rail will enter a blocked state, never producing the stop condition or releasing SDA or SCL until power is cycled.
I2C Failure when reading from the 7-bit address 0x60:
During normal operation we will see the following behavior form the device when it finds a valid address (0x40 and 0x41)
Schematic section with the CYUSB3304: Note R14 and R22 have been verified as non-stuffed:
Reference Datasheet:
https://www.cypress.com/file/141031/download
Show LessWe are currently looking into integrating the EZ-USB FX2LP USB Microcontroller in a new product and we would like to understand better how the smart SIE, which implements the Re-enumeration concept (which we find very appealing), works since we fear its complex hardware implementation might interpret into unreliability, which is essential to the product we develop. If not in any further detail, we would be grateful to at least be informed of whether the smart SIE is implemented using a processor running simple code or rather some intricate hardware.
Expecting your immediate reply.
Show LessWe are planning to use Cypress CY7C65642 USB2.0 very low power USB hub in bus powered mode for our new product. Can you share me how much is the power consumption of this Hub for 2- DS - ports to be active and both can be HS or FS. Inside the datasheet the power dissipation is shown as 432 mW. This power is not matching with the datasheet active current calculation. Expecting your immediate reply.
Show LessJust contact USB, there is a question I would like to ask
There is a registration callback function in the CYUSB3014 firmware programming:
CyU3PUsbRegisterSetupCallback(CyFxSlFIFoApplnUSBSetuPCB, CyTrue);
There are two parameters in CyFxSlFifoApplnUSBSetupCB:
Uint32_t setupdat0,
Uint32_t setupdat1
The two parameters are parsed in the function. I want to ask what these two parameters mean. What do you mean by that? ? ?
bReqType = (setupdat0 & CY_U3P_USB_REQUEST_TYPE_MASK);
bType = (bReqType & CY_U3P_USB_TYPE_MASK);
bTarget = (bReqType & CY_U3P_USB_TARGET_MASK);
Thank you!
William
Show Less- Hi.
I am in a middle of layout stage with your items HX2 and
HX3.
I am using the HX3 - CYUSB3314.
I have long trace length constrain - 4 inch for
USB2: DS3_D (pins 77 and 78) on the CYUSB3314.
When reading cypress HX3 HW design guide (AN91378)
, page16, I can see information regarding the SS lines - up to 11inch’s,length, which is great.
But no info regarding the USB2 signal length.
Could you please advise, What is the maximum allowed , trace length for USB2, with the HX3 - CYUSB3314, and especially on this specific
pins (77, 78) driver ?
thx.
nitsan.
hi all.
i can see in the begining of the data sheet requirments for externa leeprom/
then in the later pages - page 10 , there is the default descriptors .
is this means i can work with this device without extranl EEPROM ?.
the default will be according the description in the pin asingment from pages 8 and page 10?
thx.
nitsan.
Show Less