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USB Hosts Hubs Transceivers

New Contributor

Hi all,

We're developing new product with embedded HX3 USB 3 Hub (CYUSB3304) and for EMC testing need to know the max frequency. The datasheet shows the 26MHz crystal clock going to internal PLL but doesn't give the output frequency, which seems odd. Does anyone know the PLL frequency or where to find the data?

I've seen data for USB hubs from other vendors with internal clocks of around 250MHz. Is this fairly standard for all USB 3 chips?

Thanks in advance

Andrew

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Moderator
Moderator

Hello,

As per our internal documentation, the maximum frequency generated by the internal PLL is 480 MHz, the other frequencies are in the range of 30-125 MHz.

Best Regards,

Sananya

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Moderator
Moderator

Hello Andrew,

Are you enquiring about the frequencies generated by the PLL for the CPU and other internal blocks? Could you kindly give an example of any other hub which mentions the internal clock requirement as a reference?

Best Regards,

Sananys

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New Contributor

Yes I'm asking about the clocks generated internally to run the chip. I know there's a 26MHz crystal osc, and that the chip has an internal PLL, but need to know what max frequencies the internal clocks are running for EMC testing on our device.

Is there a problem letting the user know what the potential frequency emissions are going to be? I'm not asking for any information about how it's done or what tolerances, I just want to know what frequencies are generated?

I thought I'd seen a datasheet for a TI part that mentioned it used internal PLL of 250MHz, however can't find now. Regardless we need to know what the max clock frequency is for EMC testing.

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Moderator
Moderator

Hello,

As per our internal documentation, the maximum frequency generated by the internal PLL is 480 MHz, the other frequencies are in the range of 30-125 MHz.

Best Regards,

Sananya

View solution in original post

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