- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
as per datasheet page no - 6, the power input for the given part is
"CCG3PA can operate from two possible external supply sources: VBUS_IN_DISCHARGE (3.0 V–24.5 V) or VDDD (2.7 V–5.5 V). When powered through VBUS_IN_DISCHARGE, the internal regulator generates VDDD of 3.3 V for chip operation. The regulated supply, VDDD, is either used directly inside some analog blocks or further regulated down to VCCD (1.8 V), which powers majority of the core using the regulators. CCG3PA has three different power modes: Active, Sleep, and Deep Sleep. Transitions between these power modes are managed by the power system. When powered through the VBUS_IN_DISCHARGE pin, VDDD cannot be used to power external devices and should be connected to a 1-µF capacitor for the regulator stability only. These pins are not supported as power supplies. Refer to the application diagrams for capacitor connections."
so my question is can i use "VBUS_IN_DISCHARGE" and "VDDD" both as power input at same time with their respective supply limit. is that possible to power in at both the pins at same time? (it seems from above paragraph that only one power input may work at a time, but in several reference designs i found they use both pins as power input with their respective supply limits).
if this is possible that i power up the chip from both the power pins at same time, then what would be the I2C pull up voltage?
any suggestions and detailed answers will be really appreciable.
Thanks and regards,
Nisha
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Nisha,
It is not possible to use both the pins, VBUS_IN_DISCHARGE and VDDD for powering the chip at the same time.
If you use VBUS_IN_DISCHARGE for powering the chip, the internal regulator will generate VDDD of 3.3V for chip operation.
If you are using VDDD for powering the chip, it is recommended to disable the internal regulator using the function: pd_hal_disable_vreg().
If you connect both VDDD and VBUS_IN_DISCHARGE, you will be shorting the output of the internal regulator to your external power supply and back powering it which might cause damage to the chip.
Please refer to the application diagrams in the CCG3PA datasheet for both the cases of powering the chip.
May I know in which reference designs did you find that both pins are being used as power input?
Regards,
Mallika
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Nisha,
It is not possible to use both the pins, VBUS_IN_DISCHARGE and VDDD for powering the chip at the same time.
If you use VBUS_IN_DISCHARGE for powering the chip, the internal regulator will generate VDDD of 3.3V for chip operation.
If you are using VDDD for powering the chip, it is recommended to disable the internal regulator using the function: pd_hal_disable_vreg().
If you connect both VDDD and VBUS_IN_DISCHARGE, you will be shorting the output of the internal regulator to your external power supply and back powering it which might cause damage to the chip.
Please refer to the application diagrams in the CCG3PA datasheet for both the cases of powering the chip.
May I know in which reference designs did you find that both pins are being used as power input?
Regards,
Mallika
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I Refer The above reference design, please check it and let me know your views on that,
Thanks for your answer
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Nisha,
In the reference design you have mentioned, VBUS_IN_DISCHARGE is being used for powering up the chip.
VDDD is connected to 1uF and 0.1uF capacitor.
Regards,
Mallika
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
ok i get the point. That was my mistake to understand the reference design.
thanks for your answer
have a good day.