USB EZ-PD™ Type-C Forum Discussions

Hello,

CCG has two FW files (cyacd).

In SDK 3.3.1, ONE and TWO FW sizes are different.

Also, when performing File comparison, the data after Config Table data is completely different data.

CYPD3125-40LQXI_notebook_one_3_3_1_2010_0_0_0_nb.cyacd : 89KB

CYPD3125-40LQXI_notebook_two_3_3_1_2010_0_0_0_nb.cyacd : 145KB

In the previous SDK Version, it was the same size.

When I compared the data, it looked like the same data.

CYPD3125-40LQXI_notebook_one_3_2_1_1658_0_0_0_nb.cyacd : 131KB

CYPD3125-40LQXI_notebook_two_3_2_1_1658_0_0_0_nb.cyacd : 131KB

Q1) Why is the file size different in FW of the new SDK Version?

Q2) Why does the data look different in FW of the new SDK Version?

Best regards,

Kenji Takahashi

Dear all,

I'm thinking of a solution to add a Type-C to DisplayPort monitor.

That port needs the function to charge connected devices while receiving DisplayPort in alternate mode.

When I searched the reference design, I found a "Type-C-DisplayPort Cable" using CCG3.

But it was Sink, not PD Source.

Can I achieve this solution by making the following changes based on the "Type-C-DisplayPort Cable" and "Power Bank" reference designs?

-Port the Provider path of "Power Bank" to "Type-C to DisplayPort Cable".

-Replace CYPD3120 of "Type-C to DisplayPort Cable" to CYPD3121.

-Use the CCG3 Monitor Project of the EZ-PD Configuration Tool.

Best Regards,

Hidekazu Omoi

Hi,

I am trying to understand the DMC controller linker script. I understood that GCC generates the linker script and then we can use it to customize based on our requirements. I also see that the DMC project CY7C65219-40LQXIT has a custom linker script cm0gcc.ld that has been used. I am confused with some references used in the linker script.

In the above image, I see that there is a reference made to '$CYDEV_FLS_SIZE' and '$SRAM_BYTES'. But where does this exists? From where does the linker load these values? Where should I look if I want to alter them?

Regards,

Srihari Rao M

CYPD2122 is not working in dead battery mode (won’t power up) unless CC1 is connected to the Rd pin and then only in one orientation unless an external Rd is connected to CC2.

Non-functioning is expected behavior and documented when CC1 is NOT connected to the RD pin.
However, if the connector is flipped, it won’t power up with no Rd on CC2. Is this the expected behaviour?

CYPD2122 will only power up if the cable is oriented one way and CC1 is connected to the Rd pin.
If an external 5.1Kohm resistor to GND is added on CC2, the dead battery mode (powers up) works for either cable orientation.
If an external Rd is added, is there a concern with too low of a resistance on CC2 if the internal Rd applied to CC2 is activated (causing two Rd’s in parallel).

An option may be to add the FET structure externally for the dead battery Rd proported to be internal to the CYPD2122. I'd prefer not to add external dead battery logic if internal dead battery logic internally should be working.

Reference: Section 8.3 of AN210403, Hardware Design Guidelines for DRP Applications Using EZ-PD USB Type-C Controllers.

Greg

Dear,

I see from the CCG4 document that CYPD4236 can be used to implement Dual Port Power Adapter.

Are there examples for reference?

CCG4 document: https://www.cypress.com/file/220266/download

Regards,

Manu

From Table 3 and Table 4 of the data sheet Page 8, the current value is determined by ISNK_COARSE, + ISNK_FINE, but in reality, it is recognized that a maximum of 5.9A can be set by resistance voltage division.
In that case, it exceeds the PDC standard 5A, but will it become FAULT and SAFE_PWR_EN will be turned ON because of a standard violation?

Or, if I connect a 5.9A adapter (I don't think there are any products that violate such standards), will the BCR still receive power normally?

Best Regards

Q1) About OVP
It is possible to set the OVP threshold from "VBUS Overvoltage Protection" on page 3 of the data sheet.
I can't find the description of the setting method.If it is determined by the OVP setting method or the VBUS set voltage, please tell me the specific value of VBUS voltage-threshold value.
Also, please tell me the behavior when OVP is detected. (Only the FAULT output was confirmed.)

Q2) About short protection
The clamp voltage is typ 9V, but  please tell me the "Response Speed"?

Q3) About UVP
There is a description about UVP in the BCR EVK Guide (Supports on-chip OVP and UVP to protect system from faults),
I couldn't find it in the datasheet. Please tell me the existence and outline.

Q4) About soft start
The inclination of the soft start is the recognition of "SRPU" in "Table 18. Gate Driver AC Specifications". Is it correct?

Best Regards

Section 8.3 of AN210403, Hardware Design Guidelines for DRP Applications Using EZ-PD USB Type-C Controllers, states:

CCG2 has an integrated termination resistor (Rd) on the CC2 line and a dedicated RD1 resistor pin that needs to be shorted with the CC1 line of CCG2. The dead battery Rd resistors are disabled by the application firmware once the device is powered up. 
CCG2/CCG3/CCG4/CCG5/CCG5C/CCG6/CCG6F /CCG6SF/CCG6DF devices have internal active Rd terminations
that are used after the dead battery Rd resistors are disabled. 

Are the "dead battery Rd resistors" active in a CYPD2134 that is configured as a DFP with only Rp pullups connected?

If so, how long will the Rd resistors pull the CC lines low before firmware disables the "dead battery Rd resistors"?

Greg