USB EZ-PD™ Type-C Forum Discussions
Hello guys,
I am using CYPD3125 as a USB power delivery control in my circuit and I was wondering if there is a minimal limit for overcurrent protection? The chip can cut off current over 1.5A but when I try to reduce the OCP current to 1A for example, it doesn't take effect. Is the CSA for OCP adjustable for current lower than 1.5A?
Thanks in advance.
Show LessHello,
We have implemented a DRP with the controller CYPD3125 and the Mux PS8743B because the Mux PS8740B is not recommended for new design. The CYPD3125 interface to the PS8743B through the local I2C bus. In a previous conversation I have been told that I need to modify the file datamux_ctrl.c in the firmware project to make it compatible with the Mux PS8743B.
From what I understand there is three tools that can be use to customize the CYPD3125. The EZ-PD Configuration Utility, the EZ-PD CCGx Host SDK and the PSoC Creator. Can you give me a brief description of each of those tools? What is the purpose of each one?
What tool do I need to modify the file datamux_ctrl.c and compile the firmware? I assume it's the EZ-PD CCGx Host SDK.
Where can I get the default project of the CYPD3125? Is it that same that is use for the CY4531 EZ-PD CCG3 Evaluation Kit?
Thank you for helping us.
Best Regards,
Patrice
Show Less
Hi Cypress
We want to update CCG5 via HPI, and don't understand as below:
1. Can the CCG5 (HPIv2) use legacy update procedure? Or HPIv2 support Dual Firmware Mode only?
2. If the system is powered by CCG5 PD, can we disable PD ports and update? If disable the power source port, Is the system still have power?
3. In the FW Metadata Layout,
(a) How to calculate 0x00 FW checksum
(b) How to calculate 0x09-0x0C FW Size
Thank you for your answer.
Kevin
Show LessDear,
I downloaded EZ-PD Dock Reference Design v1.1 ISO from the following website:
https://www.cypress.com/documentation/reference-designs/ez-pd-ccg4-usb-type-c-monitordock-solution
After installation, I grabbed the example "CCG4_DOCK_REV05" from the following path:
C:\Program Files (x86)\Cypress\EZ-PD CCGx Dock SDK\Firmware\projects\CCG4_DOCK_REV05
When I was compiling, I encountered the following error:
How can I solve it?
Regards,
Manu
Show LessHello. Good morning.
My customer has some question with CCG7D consumer device?
Could you please give me any comment for the question?
Question#1.
Can be CCG7D-C device used for power bank application which has DRP role as power source and sink?
Question#2.
if no, as far as I know, CCG7D-C device seems to have only Rp still.
for DRP, is there any plan that have Rp, Rd on CCG7D?
Regards,
Jake
Show LessHello Community,
I'm using CCG3PA for my custom development.
My source is capable of supplying 5A current but will not be able to source Vconn.
I configured Srccapabilities to 5A in Configuration utility and built and programmed respective FW but current capability changes are not reflected in SrcCaps packet. So I believe that - For CCG3PA to advertise 5A capabilities its PDSS stack will also validate for SOP1 capabilities before advertising SrcCaps during PDC AMS. correct ?
If that is the case as my Source is unable to provide Vconn connected E-marker Cable will not be able to respond to SOP1 DiscID packets. So I need a mechanism or provision in PD Stack to bypass this SOP1 validation.
Can i get this work-around in PD stack.
Thanks and regards,
Pranay.
Show LessHi,
If I have a firmware that works for the PMG1-S1, will it also work for the more capable PMG1-S2?
If yes, what's the best way to port the firmware code from S1 to the S2?
Lastly, is it possible to load the firmware into PMG1-S1/S2 via the CC interface (like the CCG3PA)? I couldn't find more info from the PMG1 datasheet besides the SWD interface.
Thanks,
Jonathan
Hi,
On our board we have two devices CYPD5225. To configure them we are using SWD_IO/SWD_CLK pins.
On our design there is two independent signal SWD_PD1_CLK and SWD_PD2_CLK for the two CYPD5225 devices.
But the 2 devices share the same SWD_IO signal.
As the CYPD5225 does not indicate if the SWD_IO pin is an input in normal mode, is possible to have only one signal SWD_IO for the 2 CYPD5225 ?
Thank you for help,
Best Regards,
Thierry.
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Hello