USB EZ-PD™ Type-C Forum Discussions

Hello all, I am planning to design the USB-C AOC(Adaptive optical cable) using the DP Alt-mode.

As I understand, the Billboard device must present in order to negotiate the PD settings and enter Alt mode for USB-C to Displayport functionality and if a device fails to successfully enter an Alternate Mode within tAMETimeout then the device shall minimally expose a USB 2.0 interface.

I am wondering if the USB Billboard is necessary or not for entering the DP Alt-mode. Because, USB-PD(power delivery) almost communicates with CC pin between source and sink and I don't need a function to exposure USB 2.0 interface after failure of entering an Alt-mode.

I think the USB-PD chip is necessary of course, but the USB Billboard is optional for DP Alt mode. Is it right? 

Thank you.

Hi,

Hi All,

I've learned to use PSoC programmer GUI to program the target chip, please see picture below.

Now, I'm attempting to use PPCLI to download target chip.

However, I'm facing some issue with PPCLI approach.

Below is my instructions flow.

>GetPorts
<MiniProg3/1803CA0003BE
0.0494743 0 OK
OpenPort MiniProg3/1803CA0003BE returned 80004005
6.29245e-304 80004005 OK
>OpenPort MiniProg3/1803CA0003BE "C:/Program Files (x86)/Cypress/Programmer"
<
0.104875 0 OK
>HEX_ReadFile "C:\\CYPD3120-40LQXI_dp_src.hex"
<0x00020000
0.0218781 0 OK
>SetAcquireMode "Reset"
<
6.92877e-006 0 OK
>SetProtocol 8
<
0.259074 0 OK
>SetProtocolConnector 1
<
0.0749828 0 OK
>SetPowerVoltage 3.3
<
0.00172453 0 OK
>DAP_Acquire
<
0.19565 0 OK
>Erase_All
command not found
1.42353e-306 1 OK
>Program
E
Device is not in ISSP mode.
Program returned 80004005
6.19942e-006 80004005 OK
>PSoC3_EraseAll
E
This PSoC device doesn't support PSoC3_EraseAll() API
PSoC3_EraseAll returned 80004005
3.86552e-005 80004005 OK
>Verify
E
Device is not in ISSP mode.
Verify returned 80004005
1.60456e-005 80004005 OK

Q: How to use PPCli to download a Hex file to the target chip (CYPD3120-40LQXIT)???

I'm using CCG3 and CCG2 charge through dongle design.

I have successfully programmed CCG3 (3.0.2.905)  and CCG2 ( 2.2.0.287).

CCG2 appears to be working and succesfully gets PD connection and 20V from PSU.

However, I cannot get CCG3_HV_CTL signal to go high ( it is always low, it has 10K pull down on this line but GPIO should be able to go high) . Can you please confirm this firmware versions are correct for charge through dongle ? Can you please advise what other signals to check ? I have verified that CCG3 and CCG2 I2C are connected. I have 20V on drain side of AO4807( following CTD reference design exactly) , but I cannot get this signal to high to allow 20V to pass to the NB Plug ( NB Plug USB-C is always 5V).

I have a board following the CCG3 charge through dongle reference except I changed the USB-C Plug to a USB-C receptacle.

Are there software changes needed to enable the CC2 line ? I have the PSOC programmer installed and the CCG3 CTD SDK building but I don't know if any changes are required. Currently I am getting CC commands sent to the laptop but I am not getting proper response.

Hi

we are working on a bus-powered Thunderbolt device using Titan-Ridge JHL7440, CCG5C CYPD5126-40LQXIT and Bill Board Controller CY7C65215-32LTXIT. The PD firmware should be merged with the Thunderbolt firmware using Intel Imaginarium to finally store it on a single SPI Flash.

So far i have used the Thunderbolt device configuration utility and EZ-PD Configuration Utility.

I have tried the Thunderbolt device configuration utility with the instructions on https://www.infineon.com/cms/en/product/evaluation-boards/vd_usb_thunderbolt_ref/ and the provided reference designs do not include a bus-powered one. Toffee Creek seems to be close to our use-case, but no downloads are available.

The EZ-PD Configuration Utility however can customize the settings as wanted, but i have not found a possibility to generate the require bin file, that is output of the Thunderbolt device configuration utility.

Is there a possibility to generate a firmware file for a bus-powered Thunderbolt device? I am looking for a possibility like the one described by TI here: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/744271/tps65983-creating-flash-image-for-thunderbolt-3-using-tps65983

Thanks

Hi Support team, 

Please find attached the image for reference. I would like to make a configuration like the one below.

1. One upstream port (No PD required) needs to be connected to the Host processor over USB3.0 and USB2.0.
2. 7 Number of Down Stream Ports as shown in the image. 
   • 2xType C Power Delivery (2.0/3.0) & USB3.0/3.1 Gen Speed.
   • And rest of the other downstream ports shall support BC1.2 & Apple charging. Along with USB Data speed as 3.0/2.0
   • I understood the  PD and HUB integration by going through the hardware documents, like schematics, datasheets, and app notes

After reviewing the concept, we have come to the conclusion to use CY6611 EZ-USB HX3PD as Source for our product. 

Here are my queries:

1. Our system host is based on Linux. So I would like to know how to program or configure the CYUSB4347/57 using host processor via upstream ports?  Will that be possible?
2. Does CYUSB4347/57 IC come as factory preprogrammed or do we need to program? What would be the default configuration when it comes from Factory?
3. Query regarding CY6611 EZ-USB HX3PD kit
   1. I understand that "EZ-USB HX3PD Configuration Utility" can be used to customize the DS and US. Could you please help us, to configure the first two DS ports of CYUSB4347/57 as Type C PD 3.0 spec? example (20V @5A)? and US port needs to be connected to Linux OS based host and we are expecting to program or configure the HUB/PD/DMC by the Host processor.
   2. Does this software utility compatible with Linux OS?
4. We are going to reuse most of the design blocks from the CY6611 EZ-USB HX3PD kit, Do you have design files in the Altium tool?
5. The Eval Kit is using ONSEMI's NCP81239AMNTXG/NCP81239MNTXG buck-boost converters and we are seeing the part availability issues for those parts, Do you recommend any other buck-boost converters instead?. 
6. Or Does CYUSB4347/57 HUB-PD supports other power regulators that have I2C based adjustable output power?

Please feel free to ask me if you have any other queries.

Thanks & Regards

Peri

Example code:

any example code for CYPD3171 or CYPD3175

PSoC Creator IDE settings:

1. tools > options > Project Management > ARM Toolchains, set ARM MDK Generic as the actual ARMCC bin folder

2. right click on example project > build settings > Toolchain > select ARM MDK Generic, Apply & Save

3. build got error message:

--------------- Build Started: 03/26/2022 13:53:36 Project: CYPD3171-24LQXQ_cla, Configuration: ARM MDK Generic Debug ---------------
cydsfit.exe -.appdatapath "C:\Users\403283\AppData\Local\Cypress Semiconductor\PSoC Creator\4.5" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p "C:\Users\403283\Documents\PSoC Creator\new_project\CYPD3171-24LQXQ_cla\CYPD3171-24LQXQ_cla.cydsn\CYPD3171-24LQXQ_cla.cyprj" -d CYPD3171-24LQXQ -s "C:\Users\403283\Documents\PSoC Creator\new_project\CYPD3171-24LQXQ_cla\CYPD3171-24LQXQ_cla.cydsn\Generated_Source\PSoC4" -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
Elaborating Design...
HDL Generation...
Synthesis...
Tech Mapping...
Analog Placement...
Analog Routing...
Analog Code Generation...
Digital Placement...
Digital Routing...
Bitstream Generation...
Bitstream Verification...
Static timing analysis...
API Generation...
Dependency Generation...
Cleanup...
armcc.exe --cpu=Cortex-M0 --C99 --diag_style=gnu -I. -IGenerated_Source\PSoC4 --list --signed_chars -g -D DEBUG -O0 --split_sections -D__MICROLIB -c src\app\alt_mode\alt_mode_hw.c -o .\CortexM0\ARM_MDK_Generic\Debug\alt_mode_hw.o
.\config.h:52:26: Error:  #5: cannot open source input file "stack_params.h": No such file or directory
  #include <stack_params.h>
                           ^
The command 'armcc.exe' failed with exit code '1'.
--------------- Build Failed: 03/26/2022 13:53:48 ---------------

Question:

Is the default example code support building with ARMCC or not？

Should I include missing headers by hand?

The Power SDK and Host SDK does not include this CCG3 CTD upstream project.

I have one file but it says required Document manager. Can you please provide SDK file ( like power SDK for CCGx) that includes this CCG3 dongle project?

Hi.

What is the correct way to modify/maintain the CYPD4225 firmware in the year 2022?

Have I missed obvious documentation?

I see older CCGx SDK versions have a project specifically for the CYPD4225 . 

I am using PSOC creator v4.5 with windows 10, and tried to build the CYPD4225  projects in SDK v3.0.1, and v3.0.0. 
I got quite a few errors and figured I am not doing the right thing. 

Then I used the v3.5 Host SDK to build the CYPD4226 project.
I set all 3 workspace projects set to CYPD4225 

In all 3 projects, I set 'bootable' to CYPD4225 

All hell has broken loose - 

--------------- Build Started: 03/23/2022 17:10:43 Project: backup_fw, Configuration: ARM GCC 5.4-2016-q2-update Debug ---------------
cydsfit.exe -.appdatapath "C:\Users\mikep\AppData\Local\Cypress Semiconductor\PSoC Creator\4.5" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p "C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\backup_fw.cyprj" -d CYPD4225-40LQXIT -s "C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\Generated_Source\PSoC4" -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
Elaborating Design...
ADD: sdb.M0065: information: Analog terminal "VCONN_MON_P2.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2204)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Shape_2037.1)
ADD: sdb.M0065: information: Analog terminal "VCONN_MON_P1.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2202)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Shape_2036.1)
ADD: sdb.M0065: information: Analog terminal "VBUS_MON_P2.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2158)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Shape_2018.1)
ADD: sdb.M0065: information: Analog terminal "VBUS_MON_P1.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2157)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\backup_fw.cydsn\TopDesign\TopDesign.cysch (Shape_2009.1)
ADD: pft.M0124: error:
      The selected target type: Application Code and Data 2 is not valid for the current project configuration.
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
--------------- Build Failed: 03/23/2022 17:10:47 ---------------
--------------- Build Started: 03/23/2022 17:10:47 Project: CYPD4226-40LQXI_notebook, Configuration: ARM GCC 5.4-2016-q2-update Debug ---------------
cydsfit.exe -.appdatapath "C:\Users\mikep\AppData\Local\Cypress Semiconductor\PSoC Creator\4.5" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p "C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\CYPD4226-40LQXI_notebook.cyprj" -d CYPD4225-40LQXIT -s "C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\Generated_Source\PSoC4" -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
Elaborating Design...
ADD: sdb.M0065: information: Analog terminal "VCONN_MON_P2.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2204)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Shape_2037.1)
ADD: sdb.M0065: information: Analog terminal "VCONN_MON_P1.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2202)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Shape_2036.1)
ADD: sdb.M0065: information: Analog terminal "VBUS_MON_P2.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2158)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Shape_2018.1)
ADD: sdb.M0065: information: Analog terminal "VBUS_MON_P1.analog_0" on TopDesign is unconnected.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Signal: Net_2157)
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Shape_2009.1)
ADD: pft.M0086: error: Error in component: Bootloadable_1. The referenced Bootloader is invalid. Verify the Bootloader dependency is correct in the Bootloadable Component, then build project. Invalid bootloader hex file. Unable to read the hex file (C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\Bootloader\CYPD4225-40LQXI_dummy_boot.hex). The path does not exist.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Instance:Bootloadable_1)
ADD: pft.M0086: error: Error in component: Bootloadable_1. The referenced Bootloader is invalid. Verify the Bootloader dependency is correct in the Bootloadable Component, then build project. Invalid bootloader elf file. Unable to read the elf file (C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\Bootloader\CYPD4225-40LQXI_dummy_boot.elf). The path does not exist.
 * C:\Users\mikep\Documents\PSoC Creator\p\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook\CYPD4226-40LQXI_notebook.cydsn\TopDesign\TopDesign.cysch (Instance:Bootloadable_1)
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
--------------- Build Failed: 03/23/2022 17:10:51 ---------------
--------------- Build Started: 03/23/2022 17:10:51 Project: noboot, Configuration: ARM GCC 5.4-2016-q2-update Debug ---------------
The code generation step is up to date.
The compile step is up to date, no work needs to be done.
The link step is up to date, no work needs to be done.
--------------- Build Succeeded: 03/23/2022 17:10:52 ---------------