USB EZ-PD™ Type-C Forum Discussions

Hi, Sir,

Does CCG4 have unique ID inside chip?

if have, how to get the unique number ?

BR

Ivan

Hello community,

I'm using ccg3pa DVK for my product development, I'm using only main board for my development.

My requirement is :

1. Providing 3.3v on Dp and Dm lines.

Issue:

When I tried sourcing 3.3v by writing to the register " bch_det_0_ctrl /* 0x400a0700 */ ", It is giving me only ~3.1v output which is unexpected, it shall be 3.3v.

Please find respective captures below:

1. Setup being used for testing:

Scope captures:

1. with 3v3 on Dp,DM lines

2. with 0.6v on Dp,Dm lines:

Code being used:

In the above code snippet I'm using case 0 and case 1 for sourcing 3v3 on Dp,Dm lines which is not giving me the output voltage in expected range ie., supposed to be 3v3 but I'm seeing only 3.1v.

Is this voltage range expected? Anyway to source exact 3.3v on Dp,Dm lines ?

@Pranava_YN ,  This is in extension to Thread. In which you said that you're able to observe Dp voltage more than 3v, can you say me exact Dp voltage observeed ? Also please provide me your setup details ? like Is the power board is also connected or you're using only main board ?

Thanks in advance .

Best regards,

Pranay.

Hello,

I'm currently learning how to use PSoC Creator.  I need to slightly modify the project that run on the EZ-PD CCG3 evaluation kit.  I have installed EZ-PD Host SDK 3.4 and I have open up the CYPD3125-40LQXI_notebook workspace.

There is 3 projects in that workspace.  The first project is called "backup_fw", the second is called "CYPD3125-40LQXI_notebook" and the third is called "noboot".  I would like to know what are the differences between those 3 projects.

Also in the binaries folder there is 2 cyacd files.  The first is called "CYPD3125-40LQXI_notebook_one_3_3_1_2010_0_0_0_nb" and the second is called "CYPD3125-40LQXI_notebook_two_3_3_1_2010_0_0_0_nb".  I would like to know what are the differences between those 2 binaries files.

Thank you

Best Regards,

Patrice

I want to analyze the messages that occur during mobile charging with a charger that supports PPS.

ALERT, GET_STATUS, STATUS messages were confirmed like attachments.

The mobile charging operation is repeatedly charged and blocked.

I would like to confirm the cause of the incorrect charge with that message.

Please tell me the solution or the cause of the message.

Hi

I'm going to use a dp application.

There seems to be a problem between DP to HDMI and CYPD3125.

DP CHIP fails when connected to CYPD3125.

DP CHIP works normally.

As HPD is detected, communication with CYPD3125 seems to be poor.

Can we see why this is happening?

Hi All,

In the production process, our products need to be burned in batches and verified under different voltages, so miniPROG4 is not suitable for use. Segger can be used as a product burner. Therefore, how to make J-Link support CCG5 product burning?

BTW, I find a similar solution in :https://community.infineon.com/t5/USB-EZ-PD-Type-C/How-do-I-use-Jlink-to-program-CCG4-HEX-file-into-chip/td-p/113955?start=0&tstart=0 ,Does this also apply to CCG5? 

As we known, CCG3PA (3171) get TID and pass - pd compliance test.

Could you please provide us the Test Report and Eye diagram?

I am working with a CYPD6125 and am trying to use the SBU1 and SBU2 pins as a side band communications channel between two devices.  I see a few mentions in the CYPD6125 TRM that the chip contains an SBU mux that can be set so that the AUX_P and AUX_N pins are connected to the SBU pins.  However, I have not been able to find any support or examples showing how to configure that mux.

What functions or registers should I be using to set the SBU pins to be driven by the AUX pins, and is there a document or sample project that details how to use them?

Hi,

I'm in need of wiring out an extra (full speed usb) via a type-c port managed by a CCG5.

Is it safe to route a USB signal via the UART_TX_P2 (H11/J11) to the outside DPLUS/MINUS pins?

the alternative would be to use SBU1/2 and route AUX_P/_N as a debug output

didn't manage to find any electrical spec on those pins from an usb signal perspective

Hi all, 

I am studying through the CCG3 USB-C to DisplayPort Cable Solution for designing USB-C to DP cable using DP Alt-mode.

In description of the solution, it can be applied for Alt-mode standard's scenarios 2a(Source/USB-C to Sink/DP) and 2b(Source/DP to Sink/USB-C) and I have question about it.

- If I use CCG3(CYPD3120), is there difference of the firmware code between scenarios 2a and 2b? or Can I apply same configuration for both scenario 2a and 2b?

Because, I am just studying the USB-C to DP cable with an example of scenario 2a (Source/USB-C to Sink/DP) and I couldn't find some application like USB-C to DP Adapter for scenario 2b(Source/DP to Sink/USB-C) yet. So I am wondering if the same firmware code can be applied for both 2a and 2b.

Thank you.

Best Regards,

Hyunjun