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We are using the PMG1-S1 in a product and need to access the internal ADC to measure external voltages, according to the datasheet the ADC can but non...
We are using the PMG1-S1 in a product and need to access the internal ADC to measure external voltages, according to the datasheet the ADC can but none of the Modus Toolbox examples allow access to the ADC in the "Device Configuration" -> "Resources" tab.
If you have a project that uses the ADC in the PMG1-S1 please point us to it.
I inherited a board with CYPD3125-40QXIT, built by a departed engineer who followed the Cypress reference design. 2 FETs were used, en...
I inherited a board with CYPD3125-40QXIT, built by a departed engineer who followed the Cypress reference design. 2 FETs were used, enabled by VBUS_C_CTRL1,0 (pin29, 30), which I need to default to "high". Otherwise the board won't get power.
--I have not purchased a CY4531 EZ-PD CCG3 Evaluation Kit, nor do I plan to buy one. So, I can't use EZ-PD Config Utility (which may not allow me to default these 2 pins to high anyway).
--I have MiniProg3 and setup the SWD interface to the board. PSoC programmer was able to see the device.
--I have also installed PSoC Creator 4.3, and have been reading the user manual to try to figure out a way to program these two pins.
--So far I haven't found a way at all. These two pins were labeled as "power" and no manual driven popups to allow modifications. One Infineon FAE suggested to insert "pd_internal_cfet_on() function after the drive mode is set". I searched in CYPD3125-40LQXI_notebook01, and found in pdss_hal.c, line4065, pd_internal_cfet_on() is already there.
So my questions are as follows,
1. Does the device usually shipped with CYPD3125-40LQXI_notebook01 programmed?
2. If not, should I program the device again with CYPD3125-40LQXI_notebook01? Any modification needed to default the 2 pins? If so, how and where to modify?
For the CYPD4155-96BZXI, what are the VOL and VOH specifications on the VBUS FET control output pins (VBUS_P_CTRL_P1 and VBUS_C_CTRL_P1) ? Similarly,...
For the CYPD4155-96BZXI, what are the VOL and VOH specifications on the VBUS FET control output pins (VBUS_P_CTRL_P1 and VBUS_C_CTRL_P1) ? Similarly, what are the VOL and VOH specifications on VBUS_DISCHARGE_P1 and OVP_TRIP_P1? Do the specifications SID.GIO#33-#36 in the EZ-PD™ CCG4M manual (Document Number 002-11084 Rev. *C) apply to these pins in this mode (see attached)?
What is the UVP threshold on VCONN_MON_P1?
Finally, regarding VBUS_P_CTRL_P1 and VBUS_C_CTRL_P1 with the firmware that is shipped from the factory in the IC, are these signals active-low or active-high?
I have a design with two 6227 PD controllers that are connected to 4 type-c ports. I would like to select the sink path to be active on one of th...
I have a design with two 6227 PD controllers that are connected to 4 type-c ports. I would like to select the sink path to be active on one of the 4 ports.
Reading through the Host processor interface, there does not seem to be a good way to do this over i2c.
Specifically I would like to handle the following case as an example.
1. 60W PD enabled monitor is attached to controller 1, port 1 allowing charging from the monitor.
2. Later on a 90W PD charger is attached to controller 2, port 2.
In this case I would like to have a way for the EC to disable the sink path on controller 1, and enable the sink path on controller 2 when the second charger is attached to make use of the higher power.
From the interface specification it seems I would have to update the allowed port role from dual power role, to provider, however this would require issuing a port disable command first, which would disconnect the monitor alt mode.
How can I disable the sink path fet via the HPI interface without resetting the port and causing interruption to the data role?