USB EZ-PD™ Type-C Forum Discussions

A project I am working on uses a battery that runs from 29.4-22.4V to run their equipment.  We would like to add a USB Type C port with PD to it as a source (NOT A SINK, we will charge using another method) for a Laptop with a USB-C PD port as a sink so that it can charge when the laptop battery is low. What CCG kit would help me to get started on this project?

Hello,

We are considering CCG6SF as a Type-C PD controller for industrial PC.

We plan to use Windows 10 as the OS, and we have some questions about software support for CCG6SF.

- Does "Cypress EZ-PD ™ CCGx Host SDK" support CYPD6127-48LQXI?

  If not, when will it be supported?

- Is Microsft USB Connector Manager (UcmCx) provided by Cypress? 

Or does it work with Microsoft UCSI Driver?

Please answer the question.

Regards,

Shimamura

现在ccg3与MUX芯片已通过iic能够通讯，但当与电脑相连时，会依次报告  aa   84  9a（Hard Reset Sent to Port Partner）  b8（Hardware Error ）  9a  b8  9a  b8  9d  的事件，具体寄存器值见附件log.txt

抓取MUX与ccg3的IIC波形，为：20 00 20，只有一帧数据，请帮忙查找一下ccg3中是什么情况下会出现这种情况，多谢。

LOG：

[ccg3]ccg3 device register value:[ccg3] device_mode = 91
[ccg3] intr_reg = 2 [ccg3] pdport_enable = 1
[ccg3] response = 0 0 [ccg3] pd_control = 0
[ccg3] pd_status = 10036 [ccg3] type_c_status = 0
[ccg3] bus_voltage = 2e [ccg3] alt_mode_cmd[4] = 0 0 0 0
[ccg3] app_hw_cmd[4] = 0 0 0 0 [ccg3] event_mask = 7fffe
[ccg3] alt_mode_status = 0 [ccg3] port_intr_status = 0
[ccg3] pd_response = aa 0 0 0

[ccg3]ccg3 device register value:[ccg3] device_mode = 91
[ccg3] intr_reg = 2 [ccg3] pdport_enable = 1
[ccg3] response = 0 0 [ccg3] pd_control = 0
[ccg3] pd_status = 14036 [ccg3] type_c_status = 9
[ccg3] bus_voltage = 2f [ccg3] alt_mode_cmd[4] = 0 0 0 0
[ccg3] app_hw_cmd[4] = 0 0 0 0 [ccg3] event_mask = 7fffe
[ccg3] alt_mode_status = 0 [ccg3] port_intr_status = 0
[ccg3] pd_response = 84 0 0 0

[ccg3]ccg3 device register value:[ccg3] device_mode = 91
[ccg3] intr_reg = 2 [ccg3] pdport_enable = 1
[ccg3] response = 0 0 [ccg3] pd_control = 0
[ccg3] pd_status = 14036 [ccg3] type_c_status = 9
[ccg3] bus_voltage = 2d [ccg3] alt_mode_cmd[4] = 0 0 0 0
[ccg3] app_hw_cmd[4] = 0 0 0 0 [ccg3] event_mask = 7fffe
[ccg3] alt_mode_status = 0 [ccg3] port_intr_status = 0
[ccg3] pd_response = 9a 0 0 0

[ccg3]ccg3 device register value:[ccg3] device_mode = 91
[ccg3] intr_reg = 2 [ccg3] pdport_enable = 1
[ccg3] response = 0 0 [ccg3] pd_control = 0
[ccg3] pd_status = 14036 [ccg3] type_c_status = 9
[ccg3] bus_voltage = 2e [ccg3] alt_mode_cmd[4] = 0 0 0 0
[ccg3] app_hw_cmd[4] = 0 0 0 0 [ccg3] event_mask = 7fffe
[ccg3] alt_mode_status = 0 [ccg3] port_intr_status = 0
[ccg3] pd_response = b8 1 0 0 [ccg3] pd_data = 1 0

[ccg3]ccg3 device register value:[ccg3] device_mode = 91
[ccg3] intr_reg = 2 [ccg3] pdport_enable = 1
[ccg3] response = 0 0 [ccg3] pd_control = 0
[ccg3] pd_status = 14036 [ccg3] type_c_status = 9
[ccg3] bus_voltage = 2e [ccg3] alt_mode_cmd[4] = 0 0 0 0
[ccg3] app_hw_cmd[4] = 0 0 0 0 [ccg3] event_mask = 7fffe
[ccg3] alt_mode_status = 0 [ccg3] port_intr_status = 0
[ccg3] pd_response = 9a 0 1 0

I can't find a data sheet for Q1 & Q2. I also cant find a data sheet for Q3, & Q4. Does anyone know where to find these components? I searched PK616 on google and can't find it. I searched 3482 on google and can't find it.

We use CCGx SDK to develop , How to enable signed FW image for bootloading.  This is for security for bootloading.

Hello,

I have implemented the reference design for CCG3PA 45W car charger with SC 8815. For the most part, everything works great.

With an iPad Pro at 100% charge, I notice that there is a hard reset initiated by someone and then the iPad will begin charging. This only happens when the iPad is at 100% charge. At 99%, it does not have this problem.

I have attached an image of the CC log from the Car Charger FW implemented with the Car charger reference design HW. Thank you for the help.

Jeremy

/* Enable/Disable Current Foldback in QC mode */

#define QC_CF_EN

Can you explain what is the function of this QC_CF_EN define ?

In CCGx Host SDK User Guide @ https://www.cypress.com/file/432036/download , I can follow Section 5.2, which runs through and shows the high level process flow.

There are three basic steps:

• Define the configuration:
  • Reference Configuration Utility User Manual on how to create a .cyacd file.  https://www.cypress.com/file/183686/download , “Note that the XML file itself cannot be programmed to the device. A special file with “cyacd” extension is saved along with the XML file to the selected folder. This file should be used to program the configuration to the device.”
• Define the firmware program desired:

            Option 1: Use PSoC Creator to add any modifications to the base firmware for any device 

• Reference “What is required for PSoC Creator 4.x to support CCG parts?” @ https://community.cypress.com/thread/53395
• Reference “CCG2 development environment - What is the process to setup?” @ https://community.cypress.com/message/204280

Option 2: Obtain the default firmware from Cypress

• Reference “CCG Bootloader Project Files” @ https://community.cypress.com/thread/53149
• Program the device
  • **** Detailed instructions for this step are eluding me **** <<== What are the steps to merge the cyacd and hex files??
  • Merge .cyacd Configuration file into .hex Firmware file
  • Use PSoC Programmer to load into the device

Greg

How can I resolve Undefined symbol errors in an example?

I'm attempting to follow instructions of Import EZ-PD Configuration Utility C-source @ https://community.cypress.com/message/161853,

The bootloader project produces errors during build.

I started with Power Adapter example for CCG2

I added in cc_boot-pa project

I updated Components for both projects

I changed compiler in Build Settings to MDK for both projects

The following 17 errors still exist:

...

Creating archive '.\CortexM0\ARM_MDK_Generic\Debug\cc_boot-pa.a'

armlink.exe -o C:\Scratch\Try14\CYPD2134-24LQXI_power_adapter\CYPD2134-24LQXI_power_adapter.cydsn\cc_boot-pa.cydsn\CortexM0\ARM_MDK_Generic\Debug\cc_boot-pa.elf .\CortexM0\ARM_MDK_Generic\Debug\main.o .\CortexM0\ARM_MDK_Generic\Debug\usbpd_config.o .\CortexM0\ARM_MDK_Generic\Debug\cyfitter_cfg.o .\CortexM0\ARM_MDK_Generic\Debug\cymetadata.o .\CortexM0\ARM_MDK_Generic\Debug\Cm0Start.o .\CortexM0\ARM_MDK_Generic\Debug\cc_boot-pa.a --cpu=Cortex-M0 --diag_style=gnu --no_startup --library_type=microlib --map --list .\CortexM0\ARM_MDK_Generic\Debug/cc_boot-pa.map --scatter Generated_Source\PSoC4\Cm0RealView.scat --keep=Bootloader_1_Checksum --keep=Bootloader_1_SizeBytes --no_debug

ERROR: L6218E: Undefined symbol boot_jump_to_fw (referred from main.o).

ERROR: L6218E: Undefined symbol boot_start (referred from main.o).

ERROR: L6218E: Undefined symbol get_psource_ops (referred from main.o).

ERROR: L6218E: Undefined symbol load_sys_info (referred from main.o).

ERROR: L6218E: Undefined symbol pe_register_psupply_ops (referred from main.o).

ERROR: L6218E: Undefined symbol pe_state_machine (referred from main.o).

ERROR: L6218E: Undefined symbol system_init (referred from main.o).

ERROR: L6218E: Undefined symbol timer_init (referred from main.o).

ERROR: L6218E: Undefined symbol timer_start (referred from main.o).

ERROR: L6218E: Undefined symbol type_c_init (referred from main.o).

ERROR: L6218E: Undefined symbol type_c_state_machine (referred from main.o).

ERROR: L6218E: Undefined symbol typec_register_psupply_ops (referred from main.o).

ERROR: L6218E: Undefined symbol CyBtldrCommRead (referred from Bootloader_1.o).

ERROR: L6218E: Undefined symbol CyBtldrCommStart (referred from Bootloader_1.o).

ERROR: L6218E: Undefined symbol CyBtldrCommStop (referred from Bootloader_1.o).

ERROR: L6218E: Undefined symbol CyBtldrCommWrite (referred from Bootloader_1.o).

Finished: 0 information, 0 warning and 16 error messages.

The command 'armlink.exe' failed with exit code '1'.

--------------- Rebuild Failed: 05/04/2020 07:06:38 ---------------

Question is rather simple,

I notice for some USB-C designs, CC2 is simply tied to VCONN on the CCGx device (like this one here: https://www.cypress.com/documentation/reference-designs/ez-pd-ccg3-usb-type-c-displayport-cable-solution ), but what if I am looking to have a USB-C to DP dongle with Power Delivery as well?  Can CC2 be tied to VCONN or is haiving both CC lines connected a requirement for PD?

EDIT: To clarify, The requirements of our design mean we have to have a receptacle on the UFP side, not a plug.  It's really more a USB-C monitor than just a dongle (hence the need for PD as well as USC-C to DP functionality).

Thanks!