As the title says, VBUS Pch MOSFET does not turn off.
The FET is on even before the USB PD negotiation starts and does not turn off using the sink_fet_off function.
The VBUS_C_CTRL pin appears to be low all the time.
-Please let us know if you programmed any other firmware to the kit or you're using the default PD sink firmware.
-Please confirm if the FET is ON when a PD adapter is connected to J10. It would be helpful if you could provide waveforms of the CC1, CC2, VBUS, C_CTRL signals.
I have connected the USB Type-C connector to J10 and confirmed that 20V is output by PD.
I was able to rewrite the firmware to set VBUS_C_CTRL to HIGH-Z, and I confirmed that the voltage across the Gate of Q4 is 20V, but the FET does not turn off.
The FET may be faulty.
On a different note, is it possible to use VBUS_C_CTRL and VBUS_P_CTRL at the same time?
When I look at the source code, it seems to be an exclusive operation.
I removed the Q4 FET from the board, connected the Type-C connector, and output 20V PD, and J9 is outputting 20V.
In other words, it seems to always output 20V even if it is not switched by the FET.
Isn't it possible that the board design is wrong?
Can you please confirm?
I used VBUS_P_CTRL to switch the external FET.
I was able to switch it on and off without any problems.
Is this a problem with the board?
Please note that the FET will be enabled as soon as a PD adapter is connected to J10 to get 5V after which PD negotiations would start and you would see 20V on J9. Since its a PD sink implementation, only VBUS_C_CTRL is used to control the VBUS consumer path i.e. turn on/off the FET.
I was able to turn the FET off using the Cy_USBPD_Vbus_GdrvCfetOff() API and saw 0V on J9. If you're seeing 20V on J9 even after removing the FET, it could be possible that there is some fault on the board that is creating a path. Please provide your initial project with VBUS_C_CTRL set to high-Z so that I could test it on my board.
Thanks for the confirmation.
I am attaching a file that confirms the High-Z of VBUS_C_CTRL.
This is simply by adding the sink_fet_off() function to the main loop of the USBPD_SINK sample project.
In this project, I was able to confirm that the voltage between Gate and GND of Q4 is 20V, but J9 is outputting 20V.
When I connected the load in this state, I immediately disconnected the load because the voltage drop caused the FET to smoke.
Sorry for the delay in response. I couldnt see the FET turn off and 0V on J9 with your existing code but it worked after adding it in PD negotiation complete event. However, since it is a sink device and source is always attached to power it, I think the PD stack is constantly re-enabling the FET. The VBUS_P_CTRL pin is unused here by the stack so it could be why only the FET off function in your code was able to switch it off.
Please check the PD logs and waveform of the VBUS_MON test point to verify the sequence.