CCG3PA as a BC1.2 Sink(Portable Device)

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haa_4305841
Level 2
Level 2

Hi

I am trying to configure CCG3PA into BC1.2 sink and test some of the features for my internal application.

And i am using the default source code provided by cypress for the initial testing of BC1.2.

As for my primary testing i am connecting BC1.2 source device(CDP/DCP/SDP) to the type-c port of the main board and as per BC1.2 specification once the device is connected their should be initial detection (primary detection and secondary detection) & there should be D+ source voltage (0.5V to 0.7V) and  D- source voltage (0.5V to 0.7V) asserted on D+/D- lines.

But as per our observation we unable to see any changes in D+/D- lines.

So can you please suggest me how to test the BC1.2 sink.

Figure 1 : represent the working trace of BC1.2 initial detection with different sink devices.

BC1.2 DCP trace.PNG

Figure 2: represent the non working trace tested with CCG3PA.

bc1.2 dcp (with ccg3pa).PNG

Regards,

Harsha.

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1 Solution

Hello,

Please enable the LEGACY_PD_PARALLEL_OPER macro present in stack_params.h file in the power bank firmware and load the firmware (.cyacd) file using the EZ-PD configuration Utility. This should solve the problem.

Reference:

#define LEGACY_PD_PARALLEL_OPER                    (1u)

Best Regards,

Yatheesh

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11 Replies
YatheeshD_36
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Can you please let me know which firmware you are using? Is the standard power bank firmware available in the SDK or the did you modify the firmware.

Also you can refer to this thread Re: CCG3PA as a BC1.2 Sink(Portable Device)

CCG3PA supports BC1.2 sink.

Best Regards,

Yatheesh

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Hello Yatheeshk,

In case of BC1.2, if only BC1.2 source DUT connected to CCG3PA, we observed that Sink detection not happening ie primary and secondary detection is failing (Always CCG3PA acts as a Sink). But BC1.2 works only when BC1.2 Source DUT with PD support.

Is there any provision in CCG3PA to detect the BC1.2 source DUT(which do not support PD).

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Hello,

Please use the EZ-PD configuration utility, read the configuration parameters of the firmware on the device and check the following:

1) Sink settings: BC 1.2 sink is enabled and apple charging is disabled if you are not using.

pastedImage_2.png

2) Type A configuration: is enabled

Best Regards,

Yatheesh

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Hi,

As per your reference mentioned above ,we have made the configuration such that BC1.2 is enabled along with apple charging (Fig 1) and Type A configuration is enabled (Fig 2).

And we have disabled

#define CCG_TYPE_A_PORT_ENABLE                  (0u)

in the source code (stack_params.h).

Because before disabling the macro the BC1.2 state machine was entering into source mode(Fig 3) in the code flow. So do this have any effect.

Fig 1: Both BC1.2 and apple charging configuration enabled.

config control utility.PNG

Fig 2: Type A configuration is enabled

config control utility(type A config).PNG

Fig 3: BC1.2 sorce mode reference.

BC1.2 bc_stat function.PNG

Regards,

Harsha

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Hello,

Please enable the LEGACY_PD_PARALLEL_OPER macro present in stack_params.h file in the power bank firmware and load the firmware (.cyacd) file using the EZ-PD configuration Utility. This should solve the problem.

Reference:

#define LEGACY_PD_PARALLEL_OPER                    (1u)

Best Regards,

Yatheesh

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Hello Yatheeshk,

We are the enabling the LEGACY_PD_PARALLEL_OPER macro present in stack_params.h file in the power bank firmware but we are facing the same issue.

Let me explain what are the steps we are following for BC1.2(sink) validation so that you can correct me if i am wrong anywhere:

1. We are loading the firmware to the CCG3PA DVK board using mini prog and Psoc programmer utility.

Note : Before updating the firmware we are making all the configuration (ie BC1.2 is enabled along with apple charging and Type A configuration is enabled)

2. After loading the firmware we are connecting the BC1.2 source device to type-c port of CCG3PA DVK board.

3. In the mean time we are probing the D+/D- lines (TP9 and TP12) in DVK board but we are unable to see primary and secondary detection.


And if we use the source DUT which supports both PD and BC1.2 the primary and secondary detection works but if we connect only BC1.2 source DUT it is failing.

Is there any condition that if the DUT should support both PD and BC1,2 to achieve BC1.2 sink feature in CCG3PA.

Regards,

Harsha

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Hello Harsha,

Can you check the same functionality with a CDP like the ports on a PC?

The macro that I mentioned in the previous response is responsible, If the macro is disabled

i.e.

#define LEGACY_PD_PARALLEL_OPER                    (0u)

the the source device is needed to support PD.

If the macro is enabled then non PD capable device can also support BC 1.2.

I tested this on my side, The CCG3PA is successfully detecting BC 1.2 source CDP.

Can you please let me know which version of CCGx power SDK you are using? You can check this in the release notes.

Also you can try disabling the macro and testing the same again.

Please use a CDP source like ports on a laptop and test the same.

Thanks and Regards,

Yatheesh

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Hello Yatheeshk,

As per your guidelines we i am testing with CDP like the ports on a PC.But we are getting the interrupt for multiple times once the device is connected to type-c port of the DVK board (using lenovo thinkpad L480 for testing).

And for DCP devices such as QC4+ DUT's which support both PD & BC1.2, We are able to get interrupt detecting DCP device has been connected.

I have tried doing another exercise by disconnecting the CC lines of the particular DUT(QC4+) & observed their is no interrupt trigger . So as per my understanding CCG3PA is monitoring CC lines also during BC1.2 detection. And so that may be the reason for BC1.2 detection failure if only BC1.2 supported DUT is connected.

Thanks and Regards,

Harsha

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Hello Harsha,

I have tested the functionality using a Type C to Type A cable which will have a fixed termination on the cable and did not find any issues.

Best Regards,

Yatheesh

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Hello Yatheeshk,

Can you please explain in brief so that i can follow the same step what you have been following for testing. May i know the DUT's which were used for your testing so that i can correct myself if i am wrong any time.

And if you can share me the source code which you're using for this test then it will be helpful.

I am using psoc 4.2 for building my project.

Thanks and Regards,

Harsha

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Hello Harsha,

Firmware : C:\Program Files (x86)\Cypress\EZ-PD CCGx Power SDK\CCGx\Firmware\projects\CYPD3171-24LQXQ_pb

with  

#define LEGACY_PD_PARALLEL_OPER                    (1u)

CDP detection will fail if this is disabled.

DUT: lenovo T470 laptop

SETUP: CCG3PA main board type-C port is connected to type-A port of lenovo T 470 laptop.

CCG3PA board need not be externally powered. CDP detection is happening in either case.

the Detection is happening approximately every 4 seconds.

I used TP9 and TP12 tap points on the main board to measure the DP and DM voltages.

Please see the below images where the detection was captured:

1. DM line

pastedImage_1.png

2. DP line:

pastedImage_2.png

Best Regards,

Yatheesh

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