使用UART07，通过DMA进行数据发送，发送5个数据：0x79,0x91,0x04,0x71,0x01
通过逻辑分析仪截取UART07_TX的波形图如下，发出的数据不完整(只有0x79和0x71)，请问出现这个现象的原因是什么？
详细寄存器设定如下：
UART07 设定：
CPG_MFS07_UART_SCR_TXE = 0; /* UART Tx Stop */
CPG_MFS07_UART_SCR_RXE = 0; /* UART Rx Stop */
CPG_MFS07_UART_SCR_UPCL = 1; /* UART7 status initialize */
CPG_MFS07_UART_SMR = 0x00; /* Operation mode setting (Asynchronous normal mode)*/
CPG_MFS07_UART_BGR = 0x002F; /* initialize bgr 416kbps */
CPG_MFS07_UART_SCR = 0x00; /* UART7 transmission setting initialize */
CPG_MFS07_UART_ESCR = 0x00; /* Data format setting (8bit length) */
CPG_MFS07_UART_SCR_TXE = 1; /* UART Tx Start */
CPG_MFS07_UART_SCR_RXE = 1; /* UART Rx Start */
DMA0 设定：
DMA0_R_PR = 0x00; /* set dma fixed priority */
DMA0_R_DBE = 0; /* set debug no react */
DMA0_R_DB = 0x00; /* set debug behavior continue */
/* Enable DMA0 */
DMA0_R_DE = 1; /* Enable DMA */
DMA0_A0_IS = 0x00; /* Software request */
DMA0_A0_AL = 0; /* Contiguous */
DMA0_A0_BL = 0x00; /* Single transfer (SINGLE) */
DMA0_A0_BC = 0;
DMA0_A0_TC = 5;
DMA0_B0_MS = 0x01; /* Burst transfer mode */
DMA0_B0_TW = 0x00; /* Byte */
DMA0_B0_EI = 1; /* Error interrupt issuance is enabled */
DMA0_B0_CI = 1; /* Completion interrupt issuance is enabled */
DMA0_B0_PN = 0;
DMA0_SA0 = (uint32_t)(aubSendStartByte_p); /* set source address */
DMA0_DA0 = (uint32_t)&CPG_MFS07_UART_TDR; /* set destination address */
DMA0_C0_CD = 0; /* clear dma iqr */
DMA0_C0_CE = 0; /* clear dma error irq */
DMA0_D0_1_FD = 1; /* Destination address is kept fixed */
DMA0_D0_3_FS = 0; /* Source address is incremented */
DMA0_D0_3_US = 1; /* DMAi_SAn is updated with the next address after the DMA transfer is successfully completed */
DMA0_D0_3_DES = 0; /* Source address is incremented */
DMA0_D0_3_FBS = 0; /* Start address of first block of DMA transfer is set to the value stored in DMAi_SAn. Start address
of consecutive blocks is the address following the previous block last address */
DMA0_CMCHIC0_RLESEL = 0; /* CMCHIC Reload event of DMAi_CMCHICn is disabled */
DMA0_CMCHIC0_RLSLOT = 0; /* Value of DMAAn_CMCHICRDB0 register is copied to DMAi_CMCHICn at CMCHIC reload event */
DMA0_CMCHIC0_CI = 33; /* MFS ch.7 TX */
DMA0_A0_EB = 1; /* Channel is enabled */
/* External Interrupt */
EIC00_ENIR_EN0 = CLEAR; /* DISABLE External Interrupt */
EIC00_ELVR0_LA0 = 1;
EIC00_ELVR0_LB0 = 1;
EIC00_ELVR0_LC0 = 0;
EIC00_EIRCR_ERC0 = SET; /* CLEAR External Interrupt Factor */
EIC00_DRESR_DRES0 = SET; /* ENABLE DMA Request */
EIC00_ENIR_EN0 = SET; /* ENABLE External Interrupt */
DMA0_A0_ST = 1; /* Software request */
