Traveo

Hi Team,

Amber-P2LのS6J329CLSに関して、確認させて下さい。

FPD-Linkの出力差動電圧が下記レジスタで設定できますが、「Not supported」の設定(例えば、011 : 250ｍＶ) に設定した場合、

信号は何も出ないのでしょうか? それとも250mVの信号が出力されるのでしょうか?

 
Thanks and regards,

貴社IC：S6J331EJSEでEthernetを使用する際のクロックに必要な周波数公差を教えてください。

MACI/FはMIIなので、EthernetのPHYのICには±100ppm相当の水晶振動子が搭載されると思います。

MAC I/Fのデータの内にもクロックもあり、PHYのICで±100ppmの精度がある振動子を使っていれば、

マイコン側にも±100ppmのクロックがMAC I/Fにも入力され、MAC/I/Fの通信は可能となり、

マイコンのクロックとしては、±100ppmの精度のクロックは不要かと考えます。

一方で、マイコンがEthernetから入力されるデータを処理するにはやはり、EthernetのPHYと同じ

±100ppmの精度のクロックが必要になるのかとも考えていて、どちらが正しいかがわからず教えて頂けませんか。

MIIの設定や、ICのメモリ量やデータの通信量にも依存するものなのでしょうか？

MIIの±100ppmであればまだ良いですが、将来RGMIIとなると±50ppmとなり、-40～125℃の温度範囲で±50ppmを満足する水晶振動子の入手は難しいと思っています。

Hello,

Is S6J3310/S6J3320/S6J3330/S6J3340 Series Cortex-R5 architecture Armv7-R?

Best regards,

Yocchi

I'm currently working with a s6j32hel board, but since IAR (v 8.50) doesn't have that device i configured it with s6j32gel.

When a click 'Download and debug' it gives me the following warnings, how can this be fix?

Debug Log:

Mon Apr 06, 2020 11:19:39: IAR Embedded Workbench 8.50.1 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll) Mon Apr 06, 2020 11:19:39: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\Cypress\S6J3200.dmac Mon Apr 06, 2020 11:19:39: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\Cypress\TRAVEO_DEBUG.dmac Mon Apr 06, 2020 11:19:39: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\flashloader\Cypress\FlashS6J3xx_TC128KB_S384KB.mac Mon Apr 06, 2020 11:19:39: Loading the I-jet driver Mon Apr 06, 2020 11:19:39: Probe: Probe SW module ver 1.65 Mon Apr 06, 2020 11:19:39: Probe: Option: trace(Auto,size_limit=25%) Mon Apr 06, 2020 11:19:39: Probe: Found I-jet, SN=88726 Mon Apr 06, 2020 11:19:39: Probe: Opened connection to I-jet:88726 Mon Apr 06, 2020 11:19:39: Probe: USB connection verified (11538 packets/sec) Mon Apr 06, 2020 11:19:39: Probe: I-jet, FW ver 7.2, HW Ver:B Mon Apr 06, 2020 11:19:39: Probe: IJET-ARM20 adapter detected Mon Apr 06, 2020 11:19:39: Probe: Versions: JTAG=1.85 SWO=1.40 A2D=1.73 Stream=1.50 SigCom=2.44 Mon Apr 06, 2020 11:19:39: Emulation layer version 4.61 Mon Apr 06, 2020 11:19:39: JTAG clock detected: 12MHz Mon Apr 06, 2020 11:19:39: JTAG chain "TDI->TAP#1[IR=5]->TAP#0[Cortex:IR=4]->TDO" verified. Mon Apr 06, 2020 11:19:39: Notification to init-after-power-up hookup. Mon Apr 06, 2020 11:19:39: Notification to core-connect hookup. Mon Apr 06, 2020 11:19:39: Connected DAP on JTAG. Detected DP ID=0x0. Mon Apr 06, 2020 11:19:39: Connecting to TAP#0 DAP APB-AP port 1 (IDR=0x24770002) to core Cortex-R5 r1p3 at 0x80090000. Mon Apr 06, 2020 11:19:39: Debug authentication: Mon Apr 06, 2020 11:19:39:   Non-secure invasive debug not implemented Mon Apr 06, 2020 11:19:39:   Non-secure non-invasive debug not implemented Mon Apr 06, 2020 11:19:39:   Secure invasive debug enabled Mon Apr 06, 2020 11:19:39:   Secure non-invasive debug enabled Mon Apr 06, 2020 11:19:39: Debug resources: 8 H/W breakpoints, 8 watchpoints, 1 context ID breakpoints. Mon Apr 06, 2020 11:19:39: CPU status OK Mon Apr 06, 2020 11:19:39: LowLevelReset(script, delay 200) Mon Apr 06, 2020 11:19:39: Calling reset script: ResetAndStopAtEndOfBootROM Mon Apr 06, 2020 11:19:39: ----- Prepare hardware for flashloader ----- Mon Apr 06, 2020 11:19:39: Disabling Caches... Mon Apr 06, 2020 11:19:39: Configuring and initializing TCRAM (128KB)... Mon Apr 06, 2020 11:19:39: Initializing System RAM (384KB)... Mon Apr 06, 2020 11:19:40: Clear WDT Mon Apr 06, 2020 11:19:40: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\flashloader\Cypress\FlashS6J3xx_TC128KB_S384KB.out Mon Apr 06, 2020 11:19:40: Target reset Mon Apr 06, 2020 11:19:41: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\flashloader\Cypress\FlashS6J3xx_TC128KB_S384KB.mac Mon Apr 06, 2020 11:19:41: Downloaded C:\Users\rcorder1\Documents\IAR Embedded Workbench\Template 3200\arm\8.50.1\Cypress\s6j3200\S6J3260Evl\examples\template\TCFLASH Debug\Exe\template.out to flash memory. Mon Apr 06, 2020 11:19:41: 4272 bytes downloaded into FLASH (2.20 Kbytes/sec) Mon Apr 06, 2020 11:19:41: Loaded macro file: C:\Users\rcorder1\Documents\IAR Embedded Workbench\Template 3200\arm\8.50.1\Cypress\s6j3200\S6J3260Evl\examples\template\..\..\config\tcflash.mac Mon Apr 06, 2020 11:19:41: Disabling MPU and Caches... Mon Apr 06, 2020 11:19:41: Loaded debugee: C:\Users\rcorder1\Documents\IAR Embedded Workbench\Template 3200\arm\8.50.1\Cypress\s6j3200\S6J3260Evl\examples\template\TCFLASH Debug\Exe\template.out Mon Apr 06, 2020 11:19:41: LowLevelReset(software, delay 200) Mon Apr 06, 2020 11:19:41: Calling reset script: SoftwareReset Mon Apr 06, 2020 11:19:41: LowLevelReset(script, delay 200) Mon Apr 06, 2020 11:19:41: Calling reset script: ResetAndStopAtEndOfBootROM Mon Apr 06, 2020 11:19:41: 4272 bytes verified (245.40 Kbytes/sec) Mon Apr 06, 2020 11:19:41: Download completed and verification successful. Mon Apr 06, 2020 11:19:41: LowLevelReset(software, delay 200) Mon Apr 06, 2020 11:19:41: Calling reset script: SoftwareReset Mon Apr 06, 2020 11:19:41: Target reset Mon Apr 06, 2020 11:19:41: INFO: Configuring trace using 'Auto,size_limit=25%' setting ... Mon Apr 06, 2020 11:19:41: Trace: Using detected ETMv3 at address 0x8009c000 Mon Apr 06, 2020 11:19:41: Trace: ETMv3 is not powered-up (ETMCR=0x441) Mon Apr 06, 2020 11:19:41: Trace: ETMv3 powered-up OK (ETMCR=0xc40) Mon Apr 06, 2020 11:19:41: Trace: Access to detected ETMv3(architecture=3.3) initialized (CONF=0x8d254024, CTRL=0xc40, IDR=0x4104f230) Mon Apr 06, 2020 11:19:41: Trace: Using detected ETB at address 0x80001000, RAM size 0x1000 words (16KB) Mon Apr 06, 2020 11:19:41: Trace: Configured as 'ETMv3 to ETB' (SW ver:  Trace2=1.33 ETM=1.00 ETB=1.05 Deco=1.42) Mon Apr 06, 2020 11:19:41: Could not measure 'ITrgPwr' when ETM/ETB mode is active. Mon Apr 06, 2020 11:19:41: There was 1 warning during the initialization of the debugging session. Mon Apr 06, 2020 11:19:41: The stack pointer for stack 'SVC_STACK' (currently 0x00000018) is outside the stack range (0x00000A00 to 0x00000A80) Mon Apr 06, 2020 11:19:41: The stack pointer for stack 'IRQ_STACK' (currently 0x00000020) is outside the stack range (0x00000A80 to 0x00000B00) Mon Apr 06, 2020 11:19:41: The stack pointer for stack 'FIQ_STACK' (currently 0x00000028) is outside the stack range (0x00000B00 to 0x00000B80) Mon Apr 06, 2020 11:19:41: The stack pointer for stack 'UND_STACK' (currently 0x00000008) is outside the stack range (0x00000B80 to 0x00000C00) Mon Apr 06, 2020 11:19:41: The stack pointer for stack 'ABT_STACK' (currently 0x00000010) is outside the stack range (0x00000C00 to 0x00000C80)

Hi,

I'm trying to program S6J324 and S6J3360 Traveo auto R5MCU,In usually I can use FPRG.exe via JTAG using Jlink to burn TCflash.

Now I can't burn Workflash.  So I found Segger's J-Flash  support S6J324 , but it  does not have flash size .so it can not burn it.

Do you have the Segger's J-Flash device support file?  or FPRG's TcFlash  script.

I can not use Flash Memory Programmer ,Beacuse via UART is so slow。

Hi, I'm working with IAR v8.50 for S6j3200 mcu family.

My question is: Does SPI register need to be 1 in both (master and slave) in CSIO to use SPI interface?