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S6J328CL has 1-channel 4-bit x2 DDR HSSPI. I want to connect to it external QSPI Serial Flash ROM (S25FL128S or S25FL256S), for reading images to be displayed via graphic subsystem.
In datasheet "6.1 Port Description List" (p.62-63) 8 data pins and 2 select pins HSSPI are mentioned twice: in role Graphic HSSPI and role MCU HSSPI. The fundamental difference in the clock pins (G_SCLK0 - 74 pin, M_SCLK0 - 65 pin). See image (pin overlap - green, pin differences - red😞
One more moment: In hardware manual "1. Memory Map" (p.64-65) memory for HSSPI mapping in two area: Graphic subsystem (4000_0000 - 4FFF_FFFF) and CPU (8000_0000 - 8FFF_FFFF).
Do I understand correctly, that clock in flash memory in my case should be connected to G_SCLK0 Graphic HSSPI?
Does the choice (of G_SCLK0 and M_SCLK0) affect which memory area the data will be mapped to?
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Traveo
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Hi ,
Your understanding is correct, the clock pin should be selected accordingly (G_SCLK for graphics), and also the target address map will be in (4000_0000 - 4FFF_FFFF) region.
Regards,
Ashish
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Hi ,
Your understanding is correct, the clock pin should be selected accordingly (G_SCLK for graphics), and also the target address map will be in (4000_0000 - 4FFF_FFFF) region.
Regards,
Ashish
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Hi,
Thank you for answer.
Is it true that the pin selection should also be programmatically configured? In the documentation, I do not see the register where G_SCLK0 or M_SCLK0 is selected to which HSSPI clock cycle
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Hi,
Sorry for missing this. You need to check the port resource configuration for the clock pin also. Please refer series hardware manual [002-04852 Rev. *G] , chapter-11 "Port Configuration". For additional details on HSSPI, kindly refer chapter CHAPTER 52:DDR High Speed SPI Controller of Platform H/W manual (002-04854 Rev. *F).
Regards,
Ashish
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Hi,
I was innattentive, you helped me a lot. Thanks for the detailed answer.