TRAVEO™ T2G Forum Discussions
Hello,
I'm trying to run JTAG boundary scan on a Traveo T2G CYT2B73BADQ0AZSGS.
I am currently not getting any response from the device on its JTAG port.
Has anybody managed to run boundary scan tests on this device. Is there any configuration that I need to enable in order for boundary scan to run.
Thanks
Show LessDears.
I would like you to review my questions about over all of CAN FD RX Frame reception.
Please give me your opinion.
1. During CAN FD RX Frame reception, does the CAN FD RX handler of cache perform acceptance filtering on the received data frame?
2. Where exactly is the CAN FD RX Handler cache located?
3. Does the Message RAM play a role in acceptance filtering?
4. Could you provide a procedural explanation of how the acceptance filtering process operates during CAN FD RX Frame reception?
5. Please describe in detail the step-by-step process from acceptance filtering during CAN FD RX Frame reception to when the accepted data is written to the Message RAM.
Thanks and best regards,
Kevin Han.
Show LessHi All,
Whether the Cypress MiniProg4 is supported for debugging when used with GHS MULTI tool?
On the Traveo II BH controller.
dear infineon engineer or the strong community member I know a little about SPI, now i am do some experiment on SPI bus communication: my MCU is CYT2B73CAE I am using the demo example. under this path: D:\TVII_Sample_Driver_Library_6.4.0\tviibe1m\src\examples\scb\spi\Low_level_driver_master
D:\TVII_Sample_Driver_Library_6.4.0\tviibe1m\src\examples\scb\spi\Low_level_driver_slave
the master code running on one board the slave running on another same board.
i heard of some theroy that when start communication the need to pull chip selection pin low ,when transmit finished the pull it high.
the question is: in the demo code seems no code to do this.
the master i check the clk and the mosi seems right, while the connected mosi got nothing , what's more the chip select pin is always about 3V.
where am i wrong. is there any detail doc about the spi demo.
the master code can enter in the cyclic write data operation and run in to irqSCB. but get nothing from the slave. the code i am not modified, the spi relate pin is checked.
do i need to manually op the chip select pin, how can i got data smoothly from slave and run the demo normally.
Show Lesssmartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/cyt3dl-audio-volume-adjust/td-p/718019
Show LessHi.
As the title suggests, is there a FOTA routine available for the CYT2B75?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B75-FOTA-%E7%9A%84%E4%BE%8B%E7%A8%8B/td-p/719556
Show LessHi
I'm using CYT2B9.
For example, analog data is currently being input to the MCU using the P6.0 pin as ADC0_0.
I want to use it to prevent ADC data from being input to the MCU through the P6.0 pin in certain situations.
Looking at the traveo adc training document, it looks like you can connect/disconnect (switch) to the analog input pin.
Q1) Is it possible to prevent analog data from being input to the MCU for a specific ADC channel?
Q2) Can Ananlog Input Pins connect/disconnect to ADC Unit?
If not, is the Input pin always connected to the ADC Unit?
BR.
taegyunahn.
Show Less
Hi. I'm using CYT2B9.
I am using the ADC group conversion function. (sdl example: adc/GroupConversion_SwTrigger)
I am wondering if there will be any problem if I only enable/disable specific channels within the ADC group.
(Start group conversion is not performed by disabling a specific channel. Start group conversion is performed only when all channels are enabled.)
I looked at the related content on Architecture TRM and Register TRM, but I didn't exactly understand whether there was a problem.
<Architecture TRM>
<Register TRM>
Q1) Could this be a problem in the situation below? (My situation)
1. adc convserion stop
2. Disable specific channels within ADC group
3.wait...
4. Enable specific channels within ADC group
5.adc conversion start
Q2) To reconfigurate a specific channel in a group, do I need to enable/disable all channels in the group?
BR
taegyunahn.
Show LessI am running the gfx_env - flexible mode example from the "Traveo Sample driver library".
It outputs following image
(**They just enabled the test image once and then they are only updating the test pattern in the External RAM periodically. )
Where they kept this image RAM/ROM?. If I want to show any other images of my own, will I able to do that?.
Show Less