Last year I asked where I could get Demo project of Traveo 2 Starter Kit (CYTVII-B-E-1M-SK) for IAR.
I received the following answer soon.
Please kindly get in touch with your Cypress contact window for any demo project or sample code of Traveo II.
Then I asked the same question to Japanese Cypress Agency (HAKUTO).
But he says that NDA is necessary.
If you still need the demo project, please ask again to CYPRESS DEVELOPER COMMUNITY.
Could you please kindly advise me where I could get a simple demo project file (.eww) for IAR Workbench.
Traveo II CYT4B can run on 350MHZ? code is as follow:
#if (CY_SYS_PLL400M_0_FREQ == CY_SYS_PLL400M_0_350MHz)
// PLL_OUT = 24,000,000(Feco) / 3 * 125 / 5 = 200,000,000Hz
// Restriction: 400,000,000 <= Fvco <= 800,000,000
// This time, Fvco = 16,000,000 * 175 / 4 = 700,000,000.
#define CY_SYSTEM_PLL0_CONFIG_REFDIV (2UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (175UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (6UL)
#define CY_SYSTEM_PLL0_CONFIG_REFDIV (3UL)
#define CY_SYSTEM_PLL0_CONFIG_FEEDBACKDIV (125UL)
#define CY_SYSTEM_PLL0_CONFIG_OUTDIV (5UL)
#elif (CY_SYS_PLL400M_0_FREQ == CY_SYS_PLL400M_0_320MHz)
Now I’m taking the test with software logic analysis of Traveo II SDL 6.6.0 on CYTVII-B-E-176-SO.
In UART(115200Baud rate) clock part, I don’t understand the following code to configure the fractional divider.
uint64_t targetFreq = UART_OVERSAMPLING * boadrate;
uint64_t sourceFreq_fp5 = ((uint64_t)sourceFreq << 5ull);
uint32_t divSetting_fp5 = (uint32_t)(sourceFreq_fp5 / targetFreq);
Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_24_5_BIT, 0ul, ((divSetting_fp5 & 0x1FFFFFE0ul) >> 5ul), (divSetting_fp5 & 0x0000001Ful));
Could you give me your explanation or tips to clearly understand it?
Hello, trying to access (e.g. TCPWM registers) via debug probes (SWD AP1) failes with response error on CYT4BB. Further it's not possible to access successfully from embedded code (CM0+). It seems that the Range 0x40330000 .. 0xDFFFFFFF is affected. What can be the problem here? Thank you for any hint, M.Show Less
For Address 0x40520040 Register TRM says ECR. REC and TEC are read only for software. I want to understand how do ECR.RECShow Less
Using TDM functionality I'm not able to play audio. However if from cypress chip data is send to the TX port then audio plays. Can you let me know whats wrong or share same TDM code to play a audio file.Show Less
I understood that if HW cryptographic architecture especially hardware acceleration in MCU can support symetric and asymetric plus hashing , we can say that is EVITA full.
Accroding to this fact, Traveo II with HSM has EVITA full ?
Wonjin Han.Show Less