Hello,
The scenario under consideration is that both CM0+ and CM4 is accessing the Flash macro on CYT2B7x device.
The system is configured as per Case 2 of 33.1 chapter of Arch Manual (002-19314_0F_V_CYT2B_Arch-TRM).
The Blocking mode operations (program/ erase) are used in the system, the IRQ0 returns only after the processing the SROM API calls before which the flash operations are completed.
I assume that, this behavior in-turn takes care of the coherent access to flash macro, since the IPC processing will be sequential in CM0+ to activate the IRQ0 for SROM API processing.
But the blocking mode is taking longer time for operation completion and hence we would like to perform the program and erase operation in non-blocking mode.
How the non-blocking mode shall be realized from both CM0+ and CM4 and avoid the parallel access to flash macro? Since the IRQ0 returns from SROM API just after accepting the user request and the operation takes place in background.
Also there is a hint about dummy read in case of non-blocking mode access. In section 33.4.17, it is mentioned that after program and erase operation in non-blocking mode, a dummy erase operation is required, but the read operation on an erase region might lead to ECC errors, is the dummy read intended for erase operation too? or a mere cache invalidation is sufficient?
Additional Question:
I have referred the FAQ page for Flash on Traveo II, as per the question id 6.5, it is mentioned as follows,
WorkFlash
- Erase sector size is 2 KB for LS and 128B for SS.
- Program data size is 32 bits, 64 bits, 128 bits, 256 bits, 512 bits, 1024 bits, 2048 bits, and 4096 bits.
But in the architecture manual (002-19314_0F_V_CYT2B_Arch-TRM) under section 33.4.17, it is mentioned as
"For work flash the data size is always 32 bits."
@ChaitanyaV_61 : Could you please have a look and provide a hint on the above topics?
Thanks in advance,
Senthil Kumar
