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Traveo II

New Contributor

We have two variables , 1 is being updated by one Core (FBL-CM4) and are being used by other core (FBL-CM0).

2nd variable is common to both FBL CM4 and CM0.

But these variables should not be updated by other cores such as APPL CM4 and APPL CM0 ( for 1st variable FBL CM0 too ).

Could you please provide a sample code to protect these 2 variables using IPC. 

1. volatile uint32 TempState1;

2. static TempStatetype TempState2;

typedef struct


       Statevalue; //Holds enum value        

       DataFeild; //Holds uint32 value


1 Reply

Hello shivrajd1,

I have modified the IPC example that can be found in the SDL (~\TVII_Sample_Driver_Library_7.0.0\tviic2d6m\src\examples\ipc\UsingLowLevelApi).  

The example code was tested on a TVII 6M device, similar implementation can be adapted for the Body entry device as the underlying IPC architecture is similar across TVII devices. In the example, I have stored the data in the SRAM1 memory location of the 6M device, you can modify this as per your device address map or choose to store the data at any memory location as per your implementation.

For larger data (data exceeding 64 bits  i.e greater than the two 32bit data registers ), the IPC transaction can be implemented as follows:
1. Sender acquires a lock from the IPC channel
2. Sender writes the message data to the shared memory
3. Sender writes Pointer Address to data register
4. Sender generates a notification event to the receiver
5. Receiver can read the pointer from the Data register by notification event
6. Receiver reads message from address indicated by pointer
7. Receiver releases the IPC channel and also generates a release event

Acquiring the IPC structure by a sender ensures the IPC channel is 'locked' and is available only to the sender. Other cores will fail to acquire the IPC structure on reading the acquire register. 

You could test the example and let me know your observations.