- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The demo executable I have created seems to be running okay, but every now and then it gets stuck in a forever loop. It ran about 3 hours this morning before exhibiting the problem. It took as little as 15 minutes one time almost 8 hours another time. When it stops, the console terminal window shows: “MML: [ERROR] : ..\..\..\..\02_driver\basic_graphics\source\kernel\src\gccgfx_kinterrupt.c:(356): CmdSeq reported error!”
After this, it seems to be stuck down the CyGfx_DispCommit function and never returns. The Queue handling seems to think the queue is never empty.
Here is the stack:
I looked here in the Cypress community website and did not see any reported issues which seem related to this.
I have the CYTVII-C-2D-6M-CPU Traveo II evaluation board and I am using v0e60 graphics library and SDK with GHS Multi 7.1.4 and Compiler v2017.1.4.
I noticed a new release (v1e00), but the configuration was the 4MB and I had some difficulty getting this setup to work to date.
I have talked with a colleague who had noticed a similar issue on his setup in the past.
Please let me know any additional questions or thoughts on this issue.
Thanks in advance,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello GaMi_4780271
Have you set the CyGfx_ConfigSetAttribute() to Non Block? You could set the CYGFX_CONFIG_ATTR_DISPLAY_NOBLOCK to 1 and check if the function returns a busy error.
Also the call stack image seems to have been missed, could you share it again.
Regards,
Michael
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Michael,
Thank you for the feedback!
I have set to Non Block and it has been running for almost 4 hours now. It takes a long time to trigger the failure sometimes, so I will let it run over the weekend and keep an eye on it. I have it set to display a message to the terminal console if an error occurs. I have not seen an error yet.
Sorry the stack image did not get included earlier. Please find it below (trimmed to only show the failure area):
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The error tripped this weekend and the same error was provided:
MML: [ERROR] : ..\..\..\..\02_driver\basic_graphics\source\kernel\src\gccgfx_kinterrupt.c:(356): CmdSeq reported error!
After this interrupt/error, there is no return from the call to CyGfx_DispCommit().
I wonder if it is possible to get the gccgfx_kinterrupt.c file so I can more easily see this line of code and put a break point in it.
I set the MML_GDC_CONFIG_ATTR_DISPLAY_NONBLOCK to 1 in one last place.
It is in a call when opening the window and get a different error on the console terminal:
IRIS: 0x2100100b
IRIS: 0x2100100b
MML: [ERROR] : ..\..\..\..\02_driver\basic_graphics\source\user\hw\gccgfx_cmdseq.c:(719): (): Not enough space in FIFO !!!
The error happens pretty quickly and is more repeatable than the other error. Here is the call stack:
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello GaMi_4780271,
Thank you for providing the images. I am looking into this and will revert to you.
Could you provide a general description of what your application is designed to do?
Could you kindly also share your memory_map.ld file?
Regards,
Michael
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks again Michael for the follow up.
The application is Automotive cluster with a 1280x480 display.
Is there an option to provide me the gccgfx_kinterrupt.c file?
Here is the memory_map.ld file contents:
/* __DISCLAIMER_START__ */
/******************************************************************************
* (c) 2014-2020, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
* This software, including source code, documentation and related
* materials ( "Software" ), is owned by Cypress Semiconductor
* Corporation or one of its subsidiaries ( "Cypress" ) and is protected by
* and subject to worldwide patent protection (United States and foreign),
* United States copyright laws and international treaty provisions.
* Therefore, you may use this Software only as provided in the license
* agreement accompanying the software package from which you
* obtained this Software ( "EULA" ).
*
* If no EULA applies, Cypress hereby grants you a personal, nonexclusive,
* non-transferable license to copy, modify, and compile the
* Software source code solely for use in connection with Cypress' s
* integrated circuit products. Any reproduction, modification, translation,
* compilation, or representation of this Software except as specified
* above is prohibited without the express written permission of Cypress.
*
* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE. Cypress reserves the right to make
* changes to the Software without notice. Cypress does not assume any
* liability arising out of the application or use of the Software or any
* product or circuit described in the Software. Cypress does not
* authorize its products for use in any products where a malfunction or
* failure of the Cypress product may reasonably be expected to result in
* significant property damage, injury or death ( "High Risk Product" ). By
* including Cypress' s product in a High Risk Product, the manufacturer
* of such system or application assumes all risk of such use and in doing
* so agrees to indemnify Cypress against all liability.
******************************************************************************/
/* __DISCLAIMER_END__ */
/*****************************************************************************/
// Only 1MB of non-contiguous flash memory is available in PSVP and we use following hard-coded assignment for now
// IMPORTANT: only change the "code_flash" related definitions below if you know what you are doing
// CM0+ :: 0x10000000 to 0x1003ffff (256 KB)
// CM7_0 :: 0x10040000 to 0x1007ffff (256 KB)
// CM7_1 :: 0x102f8000 to 0x10377fff (512 KB)
// In addition there are 2x 64 KB (0x105F0000-0x105fffff, 0x10610000-0x1061ffff) small sectors available, but will not be used by linker file.
// Please note:
// The whole SRAM area of this device consists of several SRAM areas (SRAM0, 1, ...) each having
// its own SRAM controller. Please check the device datasheet for the exact memory to SRAM controller distribution.
// For achieving the best CM7 performance it is recommended - if possible - to ensure that data with temporal
// locality (e.g. data belonging to one task) does not span multiple SRAM controllers. Otherwise a stalling of AXI
// transactions may occur, if they are originating from the same CM7 AXI transaction ID to different SRAM controllers.
// Check that necessary definitions are available
#if ((!defined(_LINK_flash_)) && (!defined(_LINK_sram_)))
#error "Link location not defined or not supported!"
#endif
#if ((!defined(_CORE_cm0plus_)) && (!defined(_CORE_cm7_0_)) && (!defined(_CORE_cm7_1_)))
#error "Target core not defined or not supported!"
#endif
//=======================================================================================
// Following symbol and memory area definitions are used by linker_directives.ld
//=======================================================================================
DEFAULTS
{
// Cypress CAN/LIN Bootloader uses 512B at start of SRAM. This may cause issues in case of RAM build configurations, therefore this area shall be reserved.
#if defined(_LINK_sram_)
sram_start_reserve = 512
#else
sram_start_reserve = 0
#endif
//===================================================================================
// USER CONFIGURATION
//===================================================================================
// Specify how much SRAM and CODE_FLASH (starting from the first address of the respective memory) shall
// be used by CM0+ application and CM7_0 application, the rest of the memory will be automatically assigned to CM7_1 application
cm0plus_sram_reserve = 60K - sram_start_reserve
cm0plus_code_flash_reserve = 32K // minimum required
cm7_1_sram_reserve = 512
cm7_1_code_flash_reserve = 32K
//-----------------------------------------------------------------------------------
// Specify stack and heap sizes for CM0+, CM7_0 and CM7_1 application independently
cm0plus_heap_reserve = 1K
cm0plus_stack_reserve = 1K
cm7_0_heap_reserve = 200K
cm7_0_stack_reserve = 40K
cm7_1_heap_reserve = 1K
cm7_1_stack_reserve = 1K
//===================================================================================
// Constants
sram_total_size = 640K
code_flash_total_size = 6336K
cm0plus_intvec_alignment = 256
cm7_intvec_alignment = 128
ecc_init_width = 8 // Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic
sram_used_by_boot = 4K // Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations)
sram_private_for_srom = 2K // Private SRAM for SROM (e.g. API processing)
#if defined(_LINK_sram_)
// Subtract 'sram_used_by_boot' beause content will be overwritten on reset, so it should not be used for loadable sections of RAM build configurations, which are only downloaded once by debugger)
// Note: Could be removed if you ensure that no loadable section types (e.g. .text or .rodata) would be linked to this area
sram_total_size_user = sram_total_size - sram_start_reserve - sram_private_for_srom - sram_used_by_boot
#else
// Please note that 'sram_used_by_boot' is not subtracted from total size, but will have to be considered if certain sections need to preserve their content over a boot cycle
sram_total_size_user = sram_total_size - sram_start_reserve - sram_private_for_srom
#endif
// Calculation of SRAM distribution among all cores
cm0plus_sram_offset = sram_start_reserve
cm7_0_sram_offset = cm0plus_sram_offset + cm0plus_sram_reserve
// Uses the remaining space from CM0+ and CM7_1
cm7_0_sram_reserve = sram_total_size_user - cm0plus_sram_reserve - cm7_1_sram_reserve
cm7_1_sram_offset = cm7_0_sram_offset + cm7_0_sram_reserve
// Calculation of CODE_FLASH distribution among all cores
cm0plus_code_flash_offset = 0
cm7_0_code_flash_offset = cm0plus_code_flash_offset + cm0plus_code_flash_reserve
// Uses the remaining space from CM0+ and CM7_1
cm7_0_code_flash_reserve = code_flash_total_size - cm0plus_code_flash_reserve - cm7_1_code_flash_reserve
cm7_1_code_flash_offset = cm7_0_code_flash_offset + cm7_0_code_flash_reserve
// Map core dependent definition to generic name for memory and section definition
#if defined(_CORE_cm0plus_)
self_itcm_size = 0
self_dtcm_size = 0
heap_reserve = cm0plus_heap_reserve
stack_reserve = (cm0plus_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))) // Ensure that stack size is an integer multiple of ECC init width (round up)
sram_offset = cm0plus_sram_offset
sram_reserve = cm0plus_sram_reserve
code_flash_offset = cm0plus_code_flash_offset
code_flash_reserve = cm0plus_code_flash_reserve
intvec_alignment = cm0plus_intvec_alignment
#elif defined(_CORE_cm7_0_)
self_itcm_size = 64K
self_dtcm_size = 64K
heap_reserve = cm7_0_heap_reserve
stack_reserve = (cm7_0_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))) // Ensure that stack size is an integer multiple of ECC init width (round up)
sram_offset = cm7_0_sram_offset
sram_reserve = cm7_0_sram_reserve
code_flash_offset = cm7_0_code_flash_offset
code_flash_reserve = cm7_0_code_flash_reserve
intvec_alignment = cm7_intvec_alignment
#elif defined(_CORE_cm7_1_)
self_itcm_size = 64K
self_dtcm_size = 64K
heap_reserve = cm7_1_heap_reserve
stack_reserve = (cm7_1_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))) // Ensure that stack size is an integer multiple of ECC init width (round up)
sram_offset = cm7_1_sram_offset
sram_reserve = cm7_1_sram_reserve
code_flash_offset = cm7_1_code_flash_offset
code_flash_reserve = cm7_1_code_flash_reserve
intvec_alignment = cm7_intvec_alignment
#endif
}
MEMORY
{
SELF_ITCM : ORIGIN = 0x00000000, LENGTH = self_itcm_size
CODE_FLASH : ORIGIN = 0x10000000 + code_flash_offset, LENGTH = code_flash_reserve
WORK_FLASH : ORIGIN = 0x14000000, LENGTH = 0x00040000 // 256 KB
SFLASH : ORIGIN = 0x17000000, LENGTH = 0x00008000 // 32 KB
SFLASH_ALT : ORIGIN = 0x17800000, LENGTH = 0x00008000 // 32 KB
SELF_DTCM : ORIGIN = 0x20000000, LENGTH = self_dtcm_size
VRAM : ORIGIN = 0x24000000, LENGTH = 0x00400000 // 4 MB
SRAM : ORIGIN = 0x28000000 + sram_offset, LENGTH = sram_reserve
SMIF_MEMMAPPED : ORIGIN = 0x60000000, LENGTH = 0x08000000 // 128 MB
SMIF1_MEMMAPPED : ORIGIN = 0x90000000, LENGTH = 0x00200000 // 2MB of 8 MB HyperRAM e-mail from Christian Eyrich (Cypress)
ALTIA_EXTERNAL_RAM : ORIGIN = 0x90200000, LENGTH = 0x00500000 // 5MB of 8 MB HyperRAM e-mail from Christian Eyrich (Cypress)
ALTIA_HEAP : ORIGIN = 0x90700000, LENGTH = 0x00100000 // 1MB of 8 MB HyperRAM e-mail from Christian Eyrich (Cypress)
CM7_0_ITCM : ORIGIN = 0xa0000000, LENGTH = 0x00010000 // 64 KB
CM7_0_DTCM : ORIGIN = 0xa0010000, LENGTH = 0x00010000 // 64 KB
CM7_1_ITCM : ORIGIN = 0xa0100000, LENGTH = 0x00010000 // 64 KB
CM7_1_DTCM : ORIGIN = 0xa0110000, LENGTH = 0x00010000 // 64 KB
}