TRAVEO™ T2G Forum Discussions

大家好，

     最近想用keil调试cyt2bt73cae这个芯片的程序，使用mtb导出的工程只有单核应用，然后device这里显示

，这种导出的工程直接是CM4的，编译过后能够达到使用CM0启动CM4的效果？如果不能，我应该怎么做？

 当我配置了cm0plus以后，cy_m0p_image[]这个数据的含义是什么，需要我手动调用吗？ 

当我使用导出的keil工程的GPIO中断时，无法进入终端服务函数，这和我没有CM0有关系吗？

希望有人能够帮到我，感谢~

Hi, I'm using CYT4BF.

I confirmed that the Bandgap Reference circuits can be set to higher current mode or low power in the PWR_CTL2.BGREF_LPMODE register.

1) Can you explain in more detail the higher current mode and low power mode of Bandgap Reference circuits?
2) Can you tell me in what cases the PWR_CTL2.BGREF_LPMODE register is used?

BR.

taegyunahn.

we are trying to re flash the Micro Via MODUS tool .it is getting heat while flashing after 60% completed. and our tool shows power interrupt .

Error Image from our flashing tool:

please support to resolve this issue. we are struggling to Re flash the Micro . kindly share your input to resolve the issue.

Hii,

I'm using CYTVII-C-2D-6M-327-SET evaluation kit for my project.   I require information's about pinout details exposed out in dev kit and its schematic diagram .

I couldn't get those documents.  could you support on this ?

Thanks.

Hi,

 I am having the Traveo-T2G kit. CYTVII-2D-4M-216 set and the CYT3DLABHBES  cpu.

I am running the TRAVEO T2G Sample driver Library provided by infineon. I want to use freeRTOS in the project.

Previously I was using IAR V9.30.1 , in that version I could see the option in workspace to switch to the RTOS supported workspace.

Now I am using IAR v8.22.2, here no option in workpace for RTOS. Can somebody help me to run RTOS example.

Hi expert.

Recently, I encountered a case where the SFlash of the CYT2B75CAS chip was abnormally modified;

The chip abnormality manifests itself in the form of failure to boot from power-up, connecting to the chip through the compiler Attach to running targe mode, and then reading the data in the SFlash area of the chip;

And compared with the other two normal chips, found that the abnormal chip SFlash area has a lot of data is not the same, the difference area is mainly in the paragraph Flashboot code and Patches; attached is the SFlash area data I saved, and the 3 chips are the same batch;

Rather strangely, the code does not contain any calls to the API interface for modifying the SFlash, only the Erase Code Flash and Work Flash code;

What could cause the SFlash area of the chip to be abnormally modified? Regarding the area 0x17001C00 ~ 0x17006FFF, can it be abnormally tampered with when the chip is in Normal mode?

Please help the experts to analyze the possible reasons why SFlash is being modified abnormally;

Thank you~~

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/CYT2B7-SFlash-%E8%A2%AB%E5%BC%82%E5%B8%B8%E4%BF%AE%E6%94%B9/td-p/728079

Hi Team,

Couldn't find the CAN Mailbox definitions in SDL Libraries. Is there a way to configure the mailbox in TRAVEO 2 CYT2CL?

Thanks,
Pradeep

Hi,

I want to know CYT2B75CAE this controller is supporting AUTOSAR, If yes where i will get those information,

when i browse i am not able to find the information