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Sensing Technologies

Contributor

Hi,

Referring to 7.4.10 of capsense design guidelines.

pastedImage_0.png
From the capsense design guidelines document and other resources I consulted, I believe I have read mixed indications and it has become unclear if I should include to the ground central point (mentioned above):

1. All of the PSoC's VSS pins (VSSA and VSSD)

2. The ground pins of all of the PSoC's bypass capacitors

3. all of the ground connections for components like leds directly connected to the psoc pins and located in close vicinity of the psoc.

The image below illustrates my question. I have a supply ground plane on top layer (not shown in image to see the psoc and other components) and no plane on the bottom around the psoc. I am not sure if the ground pins, bypass caps and other logic components need to be isolated from supply ground along with the CIntX and capsense ground. pastedImage_1.png

It is puzzling because in the datasheet, they say VSS pin should be the central point for star connection,

but there is no VSS pin, only VSSA and VSSD on psoc4100spastedImage_0.png

Thank you for your constant support, I wouldn't have been able to learn to use capsense without you...

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1 Solution
Moderator
Moderator

Hi JeSi_4326976

As a best practice, it is recommended to connect all CapSense and analog ground connections - including hatch, Cmod, Cints - to VSSA and all digital traces such as communication lines, LEDs, etc to VSSD. The ground planes are also recommended to be kept separate and joined at the source. You can also provide an option for a ferrite bead while joining the grounds to provide additional separation If EFT/noise is not found this can also be replaced with a 0ohm resistor for short.

I would also recommend referring the Design Considerations for Electrical Fast Transient (EFT) Immunity AN, section 6.3.3.1 Ground Planes.

Best regards,
Hari

View solution in original post

1 Reply
Moderator
Moderator

Hi JeSi_4326976

As a best practice, it is recommended to connect all CapSense and analog ground connections - including hatch, Cmod, Cints - to VSSA and all digital traces such as communication lines, LEDs, etc to VSSD. The ground planes are also recommended to be kept separate and joined at the source. You can also provide an option for a ferrite bead while joining the grounds to provide additional separation If EFT/noise is not found this can also be replaced with a 0ohm resistor for short.

I would also recommend referring the Design Considerations for Electrical Fast Transient (EFT) Immunity AN, section 6.3.3.1 Ground Planes.

Best regards,
Hari

View solution in original post

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