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Hi CY Friend,
If I need 6 ASYNC SRAM connect with one chip, how to connect these srams? main chip is nxp 5777c, it has EBI interface.
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ASYNC
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Fast ASYNC
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Hello,
Our device CY62157H30 (512K Words x 16) has 16 data lines (IO0 to IO15) and 19 address lines (A0 to A18). When connected 6 of this part in depth expansion configuration, from the controller point of view it will be a larger SRAM with size 6 x (512K x 16) = 3072K x 16 and 3 additional address lines will be needed (A0 to A21) to access it.
In depth expansion configuration, data lines (IO0 to IO15), control lines (BYTE#, BLE#, BHE#, OE# and WE#) and the lower address lines (A0 to A18) should be shared between the 6 SRAMs. To select each SRAMs properly, you have to develop a logic to select (CE1# = LOW and CE2 = HIGH) each SRAM using the upper 3 address lines (A19 to A21).
Please see a related KBA here: Width and Depth Expansion of the CY7C1021 (64K x 16) SRAM .
I hope this answers your query. Please let me know, if you need any clarifications.
Thanks and Regards,
Sudheesh