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SRAM

Sophie_Wang
New Contributor II

Hi CY Friend,

If I need 6 ASYNC SRAM connect with one chip, how to connect these srams? main chip is nxp 5777c, it has EBI interface.

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1 Solution
SudheeshK
Moderator
Moderator

Hello,

Our device CY62157H30 (512K Words x 16) has 16 data lines (IO0 to IO15) and 19 address lines (A0 to A18). When connected 6 of this part in depth expansion configuration, from the controller point of view it will be a larger SRAM with size 6 x (512K x 16) = 3072K x 16 and 3 additional address lines will be needed (A0 to A21) to access it.

In depth expansion configuration, data lines (IO0 to IO15), control lines (BYTE#, BLE#, BHE#, OE# and WE#) and the lower address lines (A0 to A18) should be shared between the 6 SRAMs. To select each SRAMs properly, you have to develop a logic to select (CE1# = LOW and CE2 = HIGH) each SRAM using the upper 3 address lines (A19 to A21).

Please see a related KBA here: Width and Depth Expansion of the CY7C1021 (64K x 16) SRAM .

I hope this answers your query. Please let me know, if you need any clarifications.

Thanks and Regards,

Sudheesh

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3 Replies
SudheeshK
Moderator
Moderator

Hello,

Please provide some more details about your requirement.

1. Which is  the Cypress Async SRAM that you use in your application?

2. Are you planning to do width or depth expansion using the 6 Async SRAMs?

3. Please provide some more details about application.

Thanks and Regards,

Sudheesh

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Sophie_Wang
New Contributor II

Hi Subheesh,

Customer choose CY62157H30-45BVXA, only depth expansion.

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SudheeshK
Moderator
Moderator

Hello,

Our device CY62157H30 (512K Words x 16) has 16 data lines (IO0 to IO15) and 19 address lines (A0 to A18). When connected 6 of this part in depth expansion configuration, from the controller point of view it will be a larger SRAM with size 6 x (512K x 16) = 3072K x 16 and 3 additional address lines will be needed (A0 to A21) to access it.

In depth expansion configuration, data lines (IO0 to IO15), control lines (BYTE#, BLE#, BHE#, OE# and WE#) and the lower address lines (A0 to A18) should be shared between the 6 SRAMs. To select each SRAMs properly, you have to develop a logic to select (CE1# = LOW and CE2 = HIGH) each SRAM using the upper 3 address lines (A19 to A21).

Please see a related KBA here: Width and Depth Expansion of the CY7C1021 (64K x 16) SRAM .

I hope this answers your query. Please let me know, if you need any clarifications.

Thanks and Regards,

Sudheesh

View solution in original post

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