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SRAM

Anonymous
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 Hi,

   

               I want to know the number of the cycles till CQ/CQ# is stable.In the xilinx IP-Core it is given that 2048 cycles for the clock stable .

   

PART no :CY7C25632KV18.

   

Thanking you

   
        
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Anonymous
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        Cypress follow the QDR consortium spec 20us for the clocks to become stable. However, QDRII+ 333MHz - 450MHz, SRAMs are ok with 2048 PLL lock cycles.   

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Anonymous
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Anonymous
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        Cypress follow the QDR consortium spec 20us for the clocks to become stable. However, QDRII+ 333MHz - 450MHz, SRAMs are ok with 2048 PLL lock cycles.   

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Anonymous
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 hi

   

   Thanks 

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