SRAM Forum Discussions
The device here lists 1.65 V-2.2 V and 4.5 V-5.5 V, but not 2.2 V-3.6 V. If I want to run the device at 3 V, should I use the 5 V value as a reference?
Show LessIn the config.v file i set the define to FM25CL64B.
When I try to compile the model with ncsim, the compiler tells me that he's expecting a keyword like 'module', 'macromodule' or 'primitive' at line 381. This is where the parameters for the choosen part start.
Since there are only defines and parameters in this file the compiler output doesn't make much sense to me.
Ideas anybody?
Show LessHello
We are looking for top marking:
CY7C1061GE30-10BV1XIT
CY62187G30-55BAXI Please let me know when you will start mass production of this product.
Can you please share BSDL file for part numbers CY14B101LA-SP25XI and CY14B101LA-SZ25XI.
Comparison between the two as seen from the Logic Block Diagrams & Pin configurations as shared here in gives one to understand , there is No difference between CY7C1041GN & CY7C1041G .
NC Pins in both CY7C1041G & CY7C1041GN are Not Connected Internally to the Die.
CY7C1041G is supposed to be a part with ECC, while CY7C1041GN is identified as No ECC as for the PCN . Confusing indeed!!!!
Sharing extract of PCN155107 Last Updated: Oct 31, 2017, Issue Date: December 20, 2015, Effectivity Date: December 20, 2015
4Mb FAST and Micropower (MoBL®) Asynchronous SRAM Products: Technology Transition from 250-, 180-, 130-
and 90-nanometer to 65-nanometer Technology shared for ready reference provides the details of Process migration.
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Item |
Marketing Part Number |
Last Time Buy Date |
Last Time Ship Date |
Replacement Part Number with ECC (65nm) |
Replacement Part Number without ECC (65nm) |
13 |
CY7C1041DV33-10BVXI |
6-Jul-16 |
2-Jan-17 |
CY7C1041G30-10BVXI |
CY7C1041GN30-10BVXI |
14 |
CY7C1041DV33-10BVXIT |
6-Jul-16 |
2-Jan-17 |
CY7C1041G30-10BVXIT |
CY7C1041GN30-10BVXIT |
CY7C2663KV18 NC Pins some of the NC Pins can I connect to GND and VDDQ
In my design Iam using CY7C2663KV18 QDR-II part.
For NC Pins connection, in datasheet It is mentioned that "NC/288M and NC is not connected to the die and can be tied to any voltage level".
Can I connect some of the NC pins to GND and some of the NC Pins to VDDQ or VDD for PCB feasibility? Is it recommeded?
(1) In the RAM ARRAY section, 1M x 16/2M x 8 is shown, and depending on the input status of the control signal, either of these configurations can be changed (contents of the Truth Table).
This is the same for CY62167EV30LL-45ZXIT under the same conditions, is this correct?
Is it correct that CY62167EV30LL-45ZXIT will have the same configuration under the same conditions?
(2) CY62167G30-45ZXIT has newly added ECC ENCODE and ECC DECODE on the block diagram, how much response delay does this cause?
Or is it correct to assume that the block DATAin DRAIVERS, RAM ARRAY, and SENSE ARMS, which are also in CY62167EV30LL-45ZXIT, have a different configuration than before, and the delay is offset by the faster response speed in these areas?
(3) Just to be sure, please let us know if there are any important access timing points when using CY62167G30-45ZXIT.
(5) Just to be sure, if there are any important points in access timing when using this RAM, please let us know. If you say that it is sufficient to satisfy the AC characteristics described, that is OK.
I heard that CE must be asserted after the address is determined due to operation restrictions by other manufacturers,
I had to put in an extra WAIT to compensate for the response delay of the ECC circuit, and so on.
This is a confirmation of the problem.
(4) The recommended operating voltage of the CY62167G30-45ZXIT is 4.5 to 5.5V, whereas the CY62167EV30LL-45ZXIT
Is it correct to assume that the specifications are the same as when the product is used at 4.5 to 5.5V?
Is it correct to assume that it is the same as when using 4.5 to 5.5V?
Block diagram of CY62167G30-45ZXIT
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Hi Team,
I am working on CY62157EV30LL 45ZXi SRAM chip on imx53 processor connected through EIM interface.
1.When I write data , it hsows as written proper data but when reading it shows same 2 byte data reading for other 2 bytes also.
Example, 0x12345678 is written , when read backs it shows as 0x12341234
2. When I read for next address and so on , it shows the previously read value only like 0x12341234 as shown below
debian@arm:~$ sudo ./devmem2 0xf0000000 w 0x12345678
/dev/mem opened.
Memory mapped at address 0xb6fed000.
Value at address 0xF0000000 (0xb6fed000): 0xABCDABCD
Written 0x12345678; readback 0x12341234
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$ sudo ./devmem2 0xf0000000
/dev/mem opened.
Memory mapped at address 0xb6ff0000.
Value at address 0xF0000000 (0xb6ff0000): 0x12341234
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$ sudo ./devmem2 0xf0000004
/dev/mem opened.
Memory mapped at address 0xb6fde000.
Value at address 0xF0000004 (0xb6fde004): 0x12341234
debian@arm:~$ sudo ./devmem2 0xf0000008
/dev/mem opened.
Memory mapped at address 0xb6fbe000.
Value at address 0xF0000008 (0xb6fbe008): 0x12341234
3.Can anyine tell me what are the working timing parameters to be configured on imx side for cy6215 sram chip.
4.How to change the EIM frequency
Show LessAre there any time restrictions, etc. for BHE/BLE with respect to address signals?
For example, Liontech's SRAM LY62L409716A(https://protect2.fireeye.com/v1/url?k=31323334-501d0a38-31314cae-454441504e31-b458843b1000309f&q=1&e=e607cbae-0409-4a20-a0c6-d6eae17bbeb4&u=http%3A%2F%2Fwww.lyontek.com.tw%2Fpdf%2Flp%2FLY62L409716A-1.2.pdf%29%25E3%2581%25A7%25E3%2581%25AF%25E3%2580%2581
LB#, UB# (equivalent to BHE, BLE), etc. on P.6 Note.3
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