SRAM Forum Discussions

Hi,

CY62148G30 has an ECC function.

Furthermore, This device has not ERR terminal.

What happens if multi-bit error occurs?

However, the data sheet has the following description.

--Datasheet P.1 ------------------------------------------------------------------------

Note1. This device does not support automatic write-back on error detection.

----------------------------------------------------------------------------------------------

We don't understand the meaning of the above.

What does this Note 1. mean?

Regards,

Hello Cypress Team,

We are planning to use your SRAM as alternate to our current SRAM in our board product. But our current part has Address 17 (A17) at pin 30 and Address 18 (A18) at pin 1 from which on your device its the other way around, your A17 is at pin1 and your A18 is at pin 30. Would it still be ok to use your part as an alternate to our current part? Can it still be drop-in compatible to our current board design? Kindly advise.

Thanks.

CYRS1545AV18 is targeting space applications and the Xilinx Kintex Ultrascale is also marketed for space applications.

The CYRS1545AV18 is limited to 250 MHz clock rate.  The Xilinx Vivado Ultrascale Memory Interface Generator(MIG) for QDRII+ will not run lower than 300 MHz.

This implies that these devices are incompatible.  This was a surprise to the design team. 

Can Cypress provide any assistance or guidance.

你好，请问Cy有木有可以PIN to PIN替换VTI7512NTMI/512Kbit/TSSOP-8/SPI？这个料是SPI的接口，512Kbit容量，目前来看CY 512Kbit的SRAM只有Async Fast SRAM，PIN to PIN只有NvSRAM和FRAM，这两个价格相对SRAM贵很多，请问Cy的SRAM有木有可以直接PIN to PIN替换VTI7512NTMI/512Kbit/TSSOP-8/SPI？请帮助下，谢谢！

Hello,

We are using the obsolete part CY7C1370DV25-200AXC and looking for a functionally equivalent part. We find the CY7C1370KV25-200AXC and want to confirm that we can use it to replace the obsolete part CY7C1370DV25-200AXC.

Thank you.

We have a question about PIN183401.

When we see the DC characterization, power consumption is increasing. Also, junction temperature is changed. Please clarify why these characterization are revised before and after PIN183401.

Thank you，Shun Furusawa

Dear Sir,

We have an application use Xilinx VCU3P platform and need 512MB memory size. We use CY7C4122KV13 at previous project.

When we use RDIMM socket & design 8 pcs on the module. How to design choose different part like Async SRAM chip enable pin?

Have any reference design for this application?

Thank you.

Now Cypress note CY7C1061DV33-10ZSXI is EOL,and recommends we buy CY7C1061G30-10ZSXI,but we don't know the difference between them,I tried to look for the datasheet of both, but it was not very clear

Where can I find a data sheet for CY62155 that includes CY62155E-3XWI?

If not the full data sheet at a minimum, what does the last "5" denote?

The seventh character in the Async SRAM appears to be Bus Width.

From the CY62126 datasheet, Bus width: 6 = x 16

From the CY62157 datasheet, Bus Width: 7 = × 16

From the CY62158 datasheet, Bus Width: 8 = x 8