SRAM Forum Discussions

Hi Cypress

We need to replace the IS62WV10248EBLL-45BLI , Can you get us advice Compatible memory IC in Cypress , Thank !!

I was wondering if the act of placing the CY14B101 RTC in calibration mode, upsets the time the device is maintaining. For example, if the RTC is in calibrate mode for x milliseconds, will the RTC still maintain time for those x milliseconds. Or does the RTC lose the time it is in calibration mode?

Thank you

We want use NXP MPC5777C MCU to extend Sync. SRAM externally.

https://www.nxp.com/files-static/32bit/doc/data_sheet/MPC5777C.pdf

But the NXP MPC5777C some pins are ADMUX bus.

Cloud you guide us how to implement the connection?

Thanks,

Mitchell

Hi dear friends,

I have CY7C2670KV18-550BZI

and the marking on the parts is a bit different.

There is no country of manufacturing, but I'm not sure it should cause I use https://www.cypress.com/file/41321/download It's for 2019, but my parts are 2014 & 2018

I think the marking could be a little different, isn't  it?

Can U advise pls is it alright?

Best regards

Paolo

CY7C1356C - Ok so I am looking at the data sheet, adn I do not see how you set the address.  can I mix any of the A's around and get somewhere, my gut is saying no.  Most parts have A0 - A15 or something of that nature.  But I do not see anything like this.  More information would be nice.

We have multiple Sync. SRAM design on TOP & BOTTOM PCB for save PCB size.

Could you have any layout or guideline for reference?

I am building a homebrew CPU and have now reached the point of designing the SRAM part. I plan of using a simple 32K x 8bit static RAM (such as the Cyprus CY62256N). My concern is that the part is asynchronous but I want it to act like a synchronous part.

In the the rest of my design, registers are written to on the rising edge of the clock with the required new value already on the data lines.During the rest of the clock period the new instruction is processed and a new value might be placed on the data lines. This is fine because the register only updates on the rising edge and not later on, even though the clock happens to still be high.

I presume this approach will not work with asynchronous SRAM. I am concerned that the rising edge of the clock will update the SRAM, but if the clock happens to still be high when the value of the data lines is updated for the next instruction it will cause another update that is not wanted.

Is there some common technique to achieve what I need?

Hello I was reviewing the specs for this product and would like to know what the power dissipation is in Watts. I look forward to your response, thank you.

Hi.cypress

in the website(http://www.cypress.com/cypress-semiconductor-conflict-mineral-policy), I can't find the CMRT5.12 newly version form. the customer hope we may provide the newly CMRT5.12 version as the attachment. I only former 5.1 version via the my case number 00371009(MyCase 00371009).