SRAM Forum Discussions
The CY7C2663KV18/CY7C2665KV18 datasheet only provides the max value for the IDD (VDD supply current). What is the typical value for this supply current? Also, is read current and write current the same value? The operation current is calculated with 50% read cycle and 50% write cycle per note 29., but that's all the information we are given.
Show LessHello
The attached document obtained from the official website states that BGA has two types of internal structures.
(Stack product or regular product)
●How can I tell these apart?
●Which is the internal structure of CY7C1041GN30-10BVXI?
Best Regards
Hayato
Show LessHi
Request to share FIT Rate for the device CY14B101PA-SFXI
Regards
Sai Kiran S
ご担当者様
以下PCNの内容について確認させて下さい。
PCN205101
対象MPN:CY62146EV30LL-45ZSXI
対象MPN:CY62146GN30-45ZSXI
1.案内文面に完全に互換性有とあります。
Greatek Electronicsで製造された製品は、既存製品と形状、機能、パラメータ、および品質性能において、
部品性能に関する情報のみ互換、と言う理解でよろしいでしょうか?
2.Mold材、Lead Frame、Lead Finish、内部配線材等々異なっていることが明白な中
部品管理上・部品実装上で注意する点・異なる点は本当に無いのでしょうか?
3.RoHS,Reach,CMRT等環境上の問題や使用量に対する問題は無いのでしょうか?
4.互換性がありとは、電気的差分は0,ほぼない,少しはある
の何れを認識していればよろしいでしょうか?
以上、宜しくお願い致します。
Show LessWe are going to propose "CY62148EV30LL-45ZSXIT" as a replacement for our current production renesas SRAM "RMLV0408EGSB-4S2#HA1". while analyzing we found address line pinout A17 and A18 of the cypress part is interchanged when compare to the renesas part.
We have to clarify, is there any impact in our existing design because of this pinout change?
Please explain this.
Show LessHello,
I have a look at Cypress Flash Memory Roadmap, with family decoder, so for RAM roadmap, any decoder explanation to share? wish your answer, thanks.
Best regards,
Valley
Show LessHello,
I am having trouble getting my SRAM chip working with my FPGA board. I was wondering if anyone had any tips or extra documentation relating to these Pipelined SRAM devices. I have attached the datasheet and my Verilog code that interacts with the SRAM IC. When I load the bistream into my FPGA, if I perform a write operation, then a read operation, the data returned from the sram is correct. But if I do multiple writes, then the first piece of data returned is correct, but after that it only returns all 1's. Also when I reset the FPGA and try to read data from the first address(the one I just wrote to), it only returns all 1's. I'll outline my logic for writing to the sram below.
//Clock speed is 100Mhz
Single Write Operation:
1st positive edge of clock:
-Assert CEN
-Assert all CE
-Assert WE
-Assert ADV/LD
-write the correct address onto the address bus
2nd positive edge of clock:
-Deassert OE
-Deassert all CE
-write a dummy address onto the address bus // I don't think this is needed
3rd positive edge of clock:
-write data onto the IO bus // this is the data you want to write into the sram
-Assert all BW pins
Single Read Operation:
1st positive edge of clock:
-Assert CEN
-Assert all CE
-Deassert WE
-Assert ADV/LD
-write the correct address onto the address bus
2nd positive edge of clock:
-Assert OE
-Deassert all CE
-write a dummy address onto the address bus // I don't think this is needed
-Read the data on the IO bus
Currently, I am only trying to go from a deselected state -> read or write -> deselected.
I have no idea what is wrong so I am wondering if I am missing a setup thing or something because I don't think it is writing to the SRAM at all. It should also be noted that I am developing this on a custom FPGA board that I designed myself so there very well could be an issue with how I connected it(See schematic attached). There are a lot of variables at play here so if anyone has any ideas about how my code is wrong, it would be greatly appreciated.
Thank you for your help!
-Ryan
Show LessHi Team,
I am looking for a parallel synchronous DPRAM with Interrupt. I zeroed down to CY7C09389V but it seems that this component is now obsolete. Can you please suggest any equivalent component or list of components?
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