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SRAM

Anonymous
Not applicable

 In CY7C2564XV18 datasheet, Idd is specified for 50% read and 50% write cycles (note 24 on p.20).

   

The QDRII+ having dedicated interfaces for read and write, one can push it to 100% read and 100% write cycles.  Then, what happens to the core power?  Does Idd double?

   

Question holds for lower usage.  What Idd to expect at 10%?

   

Regards,

   

Frederic

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1 Solution
PriteshM_61
Employee

 Hi,

   

    

          

   

QDR-II+ memories can perform read and write operation in parallel but internally memory cell can execute a single operation (Read or Write) at the time. So we are considering the worst case which is 50% read and 50% write for internal memory array.

   

Cypress does not specify Idd values based on different reads and writes operation ratio as there is a distribution associated with the same. However, we focus on the worst case situation (Idd max) so that we can guarantee Idd (MAX) values.

   

    

          

   

Thanks,

   

Pritesh

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2 Replies
PriteshM_61
Employee

 Hi,

   

    

          

   

QDR-II+ memories can perform read and write operation in parallel but internally memory cell can execute a single operation (Read or Write) at the time. So we are considering the worst case which is 50% read and 50% write for internal memory array.

   

Cypress does not specify Idd values based on different reads and writes operation ratio as there is a distribution associated with the same. However, we focus on the worst case situation (Idd max) so that we can guarantee Idd (MAX) values.

   

    

          

   

Thanks,

   

Pritesh

View solution in original post

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Anonymous
Not applicable

I understand that 50-50% usage specified in note 24 is related to the internal memory operation, not to its external interfaces.

   

I'll consider the values specified for Idd as the worst possible consumption.

   

Thanks for that quick answer.

   

Frederic

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