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SRAM

LIWA_4389481
New Contributor

Hello, Cypress:

             we are considering CY7C2665KV18 in the new design, and I would refer to xilinx VCU110 development board

for CY7C2663 was used inside.

            could the schematic lib of  CY7C2665KV18 provided to me?

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi,

Please find the schematic file for CY7C2665KV18.

Choosing between QDR II+ and QDR IV should be based on the application requirements. Cypress’s high-bandwidth QDR-IV SRAMs are designed for high-speed performance and they satisfy demanding network functions, such as updating statistics, tracking flow states, scheduling packets, and performing table lookups.

QDR-II/II+ SRAMs are ideal for systems with back-to-back Read-Write operations. QDR-II/II+ SRAMs are also recommended when pin count must be optimized and is facilitated by double data rate operation of the buses. The appropriate choice is determined by the actual read to write ratio and desired burst length. So you can check these points briefly with your application requirements and select the device as per requirement.

Regards,

Pradipta.

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3 Replies
LIWA_4389481
New Contributor

As I had ever used CY7C4142KV13 ever, the max clock period is 3.33ns, so the lowest work frequency of CY7C4142 is 333MHz? do you suggest  me use CY7C4142KV13 work at low speed for example:400MHz,500MHz in the module, or use CY7C2665KV18?

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PradiptaB_11
Moderator
Moderator

Hi,

Please find the schematic file for CY7C2665KV18.

Choosing between QDR II+ and QDR IV should be based on the application requirements. Cypress’s high-bandwidth QDR-IV SRAMs are designed for high-speed performance and they satisfy demanding network functions, such as updating statistics, tracking flow states, scheduling packets, and performing table lookups.

QDR-II/II+ SRAMs are ideal for systems with back-to-back Read-Write operations. QDR-II/II+ SRAMs are also recommended when pin count must be optimized and is facilitated by double data rate operation of the buses. The appropriate choice is determined by the actual read to write ratio and desired burst length. So you can check these points briefly with your application requirements and select the device as per requirement.

Regards,

Pradipta.

View solution in original post

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LIWA_4389481
New Contributor

Hi, Pradipta:

     had got your response, thanks.

Regards

Li

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