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SRAM

Max_Power
New Contributor II

In one design we use the SRAM CY62167EV30LL-45BVXI with 65nm technology.

The data sheet CY62167EV30_MOBL_16_MBIT_1M_X_16_2M_X_8_STATIC_RAM.pdf says
"The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. "

A date is read from an address from the FLASH and this date is stored in the same address in the SRAM. Then the address will not be toggled.

Is it possible during this process that the SRAM goes into automatic power down?

How is the timing for the required address toggling defined?

The case would be very bad if the same address in the SRAM was written several times with different dates in succession. The SRAM is permanently chipselect with /CE1 and write is / WE controlled.
The last date is then not written because the SRAM has gone into power down due to the missing address toggling.
The SRAM can only be powered up again with a chip select /CE1=0 to 1 to 0.

Are 2 write commands possible in succession on this SRAM?

Hence my question about the time in ns at which the address must absolutely change so that the SRAM does not go into power down. This time is not in the data sheet. /CE1 is permanently low.

 

With best regards
Max Power

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi Max,

We have discussed your concern with the product engineer as well and you can perform consecutive write into same address without any address toggle. Please  refer to the deselect condition in DC char table. This is applicable only when device is deselected (your concern).

Thanks,

Pradipta.

View solution in original post

4 Replies
PradiptaB_11
Moderator
Moderator

Hi Max,

When the CE1 is asserted (low) the chip will not be deselected at all and will not go into standby. It will not go into automatic power down. You can also write as many number of times successively as your application requires.

Thanks,

Pradipta.

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Max_Power
New Contributor II

Hello PradiptaB_11,

This statement does not satisfy me.

"The device also has an automatic power down feature that reduces power consumption by 99 percent
when addresses are not toggling. "

What about the statement "addresses are not toggling".
According to the data sheet, this is independent of /CE1=0.
With /CE1=0 you can only wake up if it were in power down before.
Nowhere is it described that with /CE1=0 no power down is possible.

I have to accept that because nothing else is described in the data sheet. Therefore, I cannot use this uncommitted property from you PradiptaB_11.

OR

I need to get a full description of this automatic power down when addresses are not toggling feature in order to accept it.
Without this statement, I cannot support multiple writes without changing the address with changing dates.
I have to design the firmware for the control of the µC system to the SRAM in such a way that an address change must take before every write command, so that no errors are guaranteed.

I ask for one more comment.

 

With best regards
Max Power

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PradiptaB_11
Moderator
Moderator

Hi Max,

We have discussed your concern with the product engineer as well and you can perform consecutive write into same address without any address toggle. Please  refer to the deselect condition in DC char table. This is applicable only when device is deselected (your concern).

Thanks,

Pradipta.

View solution in original post

Max_Power
New Contributor II

Hello PradiptaB_11,

Thanks for that answer.

greeting
Max Power

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