We have been using the CP62167EV30LL-45BVXI memory on our modules since 2014.
We were affected by the AN66311 in 2014
"TIMING RECOMMENDATIONS FOR BYTE ENABLES AND CHIP ENABLES IN MOBL (R) SRAMS - AN66311"
After this bug was fixed by Cypress and we received new CP62167EV30 components, the error on our modules disappeared.
Until now in 2021.
Memory errors are now increasingly occurring on our assemblies during the final inspection, failure rate approx. 50%. After asking us, we were able to determine that Cypress has changed this SRAM from 90nm technology to 65nm technology.
I looked at the data sheet and compared it with the old one and couldn't see any significant changes. An analysis of the memory accesses, timing, etc. on the defective assemblies has not been successful either.
If defective modules from production are equipped with the previous 90nm CP62167EV30LL-45BVXI, then they will function properly again.
Could it be that by changing the technology from 90nm to 65nm, the old bug from AN66311 was redesigned.
I am grateful for a quick answer.
The bug reported in the AN66311 was fixed and it is unlikely that you will be affected by it in the newer lots or in the new technology node of 65 nm. It may be an issue related to some timing violations but to be sure we will need to check this thoroughly.
1)Can you share with us the schematics of the memory portion ?
2) Can you send us the read and write scope shots for a failing unit and a old passing unit ?
If you are not okay to sharing these on public forum we will move to a tech support case.
I noticed a malfunction of the SRAM with 65nm technology on some assemblies.
This error is very rare, but I can reproduced very well.
The µC continuously writes several dates to different addresses in the SRAM. A write process is always ended with a high on the /WR signal. This high lasts 18ns, then /WR becomes too low again.
By reading it back, you can see that sometimes the wrong date has been written into an address.
My guess is that the high duration of the /WR signal is too short.
How long must the /WR signal be high so that the write command does not become invalid? Unfortunately, this time is not in the data sheet. I've already checked the other timings, they're all ok.
Does the /WR signal violate the specification of F_max = 1 / t_RC = 1 / 45ns?
What is the required high duration for the /CE signal. In my application is this a maximum of 40ns.
These times actually have to be specified because the Logic gate delay times are available in the SRAM itself.
For us to evaluate better we will need to have a look at the scope shots for the read and write operations as requested in our previous response. It is difficult for us to comment anything on your observations without checking them ourselves.