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A quick question regarding the DOFF# pin for the QDR-II+ SRAM, part number CY7C25652KV18:
Does the DOFF# pin use HSTL logic levels, as given in the Vih and Vil of Table xx?
Or does DOFF# require other (CMOS?) logic levels as suggested by the wording in the description of DOFF# in "Pin Definitions":
"Connecting this pin to ground turns off the PLL inside the device. The timings in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 k or less pull up resistor."