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SRAM

AbPe_3615041
New Contributor

I am interfacing QorIQ Processor with SRAM memory (CY62167G18-55ZXI). I am unable to know how to interface BLE#(Byte Low Enable) and BHE#(Byte High Enable) signals present on SRAM to the processor.

CY62167G18-55ZXI
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1 Solution
PradiptaB_11
Moderator
Moderator

Hi Abhijit,

Using any external logic or not will depend on you.

You may assert the two pins BHE# and BLE# by connecting to GND and use the WE# and OE# and CE# pins to control the chip. WE# pin can control the writes, OE# pin can control the reads while CE# can used to select and deselect the chip.

You may want to use the flexibility provided by the BHE# and BLE# pins and if you do not have any dedicated pins for it you can connect any GPIO pins to it and formulate the code/Software in a desired fashion.

Kindly refer to the truth table on page 16 of the datasheet which shows the logic state of all the control signals and the operation performed by the device.

Thanks and Regards,

Pradipta.

View solution in original post

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PradiptaB_11
Moderator
Moderator

Hi Abhijit,

It will be based on your application. For instance first you will need to decide that in which configuration you want to use the memory.Tie the BYTE pin in the 48-pin TSOP I package to VCC to use the device as a 1 M ×16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8 SRAM by tying the BYTE signal to VSS. In the 2 M × 8 configuration, pin 45 is the extra address line A20, while the BHE, BLE, and I/O8 to I/O14 pins are not used and can be left floating.

Thanks and Regards,

Pradipta.

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AbPe_3615041
New Contributor

Hi Pradipta,

Assuming that I will be using x16 SRAM, as per the waveform of the SRAM the BLE# and BHE# signals will be pulled while the read and write operations are in progress.

The BYTE# signal is pulled high in our application as we are going to work in x16 mode. But for the signals BLE# and BHE# we need controlled signal from the processor interface. My concern is that our processor does not have any dedicated signals for selecting the low byte and high byte. Do I have to use any external logic for selecting these signals?

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PradiptaB_11
Moderator
Moderator

Hi Abhijit,

Using any external logic or not will depend on you.

You may assert the two pins BHE# and BLE# by connecting to GND and use the WE# and OE# and CE# pins to control the chip. WE# pin can control the writes, OE# pin can control the reads while CE# can used to select and deselect the chip.

You may want to use the flexibility provided by the BHE# and BLE# pins and if you do not have any dedicated pins for it you can connect any GPIO pins to it and formulate the code/Software in a desired fashion.

Kindly refer to the truth table on page 16 of the datasheet which shows the logic state of all the control signals and the operation performed by the device.

Thanks and Regards,

Pradipta.

View solution in original post

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AbPe_3615041
New Contributor

Hi Pradipta,

Thank you for helping. Your description has helped a lot in clearing my doubts regarding BHE# and BLE# interfacing.

The chip that I am using has two CS# (chip select) signals CS1# and CS2. I am currently having only one chip select from the processor. I have connected CS# from processor directly to CS1# and then to CS2 with a NOT gate. Is this the correct implementation?

--

Regards

Abhijit Pethkar

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PradiptaB_11
Moderator
Moderator

Hi Abhijit,

Yes, you can implement dual CS with a not gate also.

You can also connect CS2 permanently to VCC or logic high. By doing this You can control the Chip by CS1# pin only as CS2 will always be asserted.

Thanks and Regards,

Pradipta.

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AbPe_3615041
New Contributor

Hi Pradipta,

Thank you for your help. The case can be closed from my end.

--

Regards

Abhijit Pethkar

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