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SRAM

RyBu_4832581
New Contributor II

Hello,

I am having trouble getting my SRAM chip working with my FPGA board. I was wondering if anyone had any tips or extra documentation relating to these Pipelined SRAM devices. I have attached the datasheet and my Verilog code that interacts with the SRAM IC. When I load the bistream into my FPGA, if I perform a write operation, then a read operation, the data returned from the sram is correct. But if I do multiple writes, then the first piece of data returned is correct, but after that it only returns all 1's. Also when I reset the FPGA and try to read data from the first address(the one I just wrote to), it only returns all 1's. I'll outline my logic for writing to the sram below.

//Clock speed is 100Mhz

Single Write Operation:

1st positive edge of clock:

     -Assert CEN

     -Assert all CE

     -Assert WE

     -Assert ADV/LD

     -write the correct address onto the address bus

2nd positive edge of clock:

     -Deassert OE

     -Deassert all CE

     -write a dummy address onto the address bus // I don't think this is needed

3rd positive edge of clock:

     -write data onto the IO bus // this is the data you want to write into the sram

     -Assert all BW pins

Single Read Operation:

1st positive edge of clock:

     -Assert CEN

     -Assert all CE

     -Deassert WE

     -Assert ADV/LD

     -write the correct address onto the address bus

2nd positive edge of clock:

     -Assert OE

     -Deassert all CE

     -write a dummy address onto the address bus // I don't think this is needed

     -Read the data on the IO bus

Currently, I am only trying to go from a deselected state -> read or write -> deselected.

I have no idea what is wrong so I am wondering if I am missing a setup thing or something because I don't think it is writing to the SRAM at all. It should also be noted that I am developing this on a custom FPGA board that I designed myself so there very well could be an issue with how I connected it(See schematic attached). There are a lot of variables at play here so if anyone has any ideas about how my code is wrong, it would be greatly appreciated.

Thank you for your help!

-Ryan

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1 Solution
RyBu_4832581
New Contributor II

Pradipta,

After a few days of tinkering I think I have figured it out. My basic idea was to go from deselected -> selected -> read or write -> deselected.

This process seems to work just fine for write operations, but for read operations, the data lines are tristated upon emerging from a deselected state. But what I found from tinkering is that it takes several clock cycles for the device to become ready to output data.

I still need to do a couple of days of testing, but I think this was my issue, I'll set this question to answered if everything else checks out.

Thanks again for taking a look at this!

-Ryan

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3 Replies
PradiptaB_11
Moderator
Moderator

Hi

The schematics look ok. I will check your code and try to look for any issues.

Thanks,

Pradipta.

RyBu_4832581
New Contributor II

Pradipta,

Thank you for taking a look at the schematic, and for your help! I am fairly new to Verilog, so any help is greatly appreciated.

Let me know if you want to look at anything else!

-Ryan

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RyBu_4832581
New Contributor II

Pradipta,

After a few days of tinkering I think I have figured it out. My basic idea was to go from deselected -> selected -> read or write -> deselected.

This process seems to work just fine for write operations, but for read operations, the data lines are tristated upon emerging from a deselected state. But what I found from tinkering is that it takes several clock cycles for the device to become ready to output data.

I still need to do a couple of days of testing, but I think this was my issue, I'll set this question to answered if everything else checks out.

Thanks again for taking a look at this!

-Ryan

View solution in original post

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