CY7C4141 (QDR-IV) without QKB0 & QKB1 clock output

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chsi_4622291
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CY7C4141 have enabled port A and port B by asserting A[12:11]=11 at reset rising edge (assured by Oscilloscope). But we test the SRAM without QKB0 , QKB1 output all the time , and QKA0,QKA1 are normal.

Is that state normalized? It seems the QDR-IV be put into Fixed Port Mode or Only Port A Enable mode, why?

Now the CY7C4141 fails on Write deskew.

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Hi Chen,

I suggest you to use our AN on QDR IV. It will give you an idea on the clocking signals description (section 3.1) and the deskew sequence(section 3.3). Kindly follow section 3.3 step by step as described let us know if you face any issues.

https://www.cypress.com/file/46581/download

Thanks,

Pradipta.

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