CY7C1411KV18 input clocks (K and K/) 是差分时钟还是伪差分？

[GeHe_4772401]

1网站有信息提到input clocks (K and K/) 是伪差分？在对应的Datasheet中没有找到对应的描述？

2和FPGA 配套使用时，这些时间应该连接至真差分引脚还是伪差分引脚？

[SudheeshK · Accepted solution]

Hello,

I hope the below KBA will answer your query.

K/K# Clocks Routing for QDR®II/II+/DDRII/DDRII+ SRAMs – KBA89248

Please feel free to ask if you need any clarifications.

Thanks and Regards,

Sudheesh