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SRAM

New Contributor

HI,

I am using CY7C1041G30-10ZSXI SRAM  which is interfaced with microsemi samrt fusion 2 FPGA. In interfacing the part to FPGA, I am not sure any kind of termination (like series resistor, as of now no terminations are considered as it cmos output and inputs) is required here to reduce the reflection between the device other than length matching (+/-10mils in FR4 board) and impedance (50+/-10%) control in PCB. Maximum operating frequency considered as 100MHz

Kindly recommend any terminations are to be considered for this particular interface and let me know if any other considerations to be taken for reducing the reflection.

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Moderator
Moderator

Hi,

If you have matched the load impedance to the line's characteristic impedance it will suffice. Also i am attaching SRAM board design guidelines along with it.

https://www.cypress.com/file/38651/download

Thanks,

Pradipta.

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Moderator
Moderator

Hi,

If you have matched the load impedance to the line's characteristic impedance it will suffice. Also i am attaching SRAM board design guidelines along with it.

https://www.cypress.com/file/38651/download

Thanks,

Pradipta.

View solution in original post

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New Contributor

Hi,

Thanks for quick response it real helps my activities, one last question i am new to using memory device so please don't mind me asking these regarding terminations.

  • Any  pull up or pull down resistors are required for Address and data groups for any reason to avoid floating state or if CE is pulled high will be sufficient info for reliable communication.
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