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SRAM

chku_3524716
New Contributor

Hi,

We are using LPC4088 based custom board interfacing external nor-flash(SST39vf3201), SRAM(CY62157EV30LL) & FPGA on static memory CS3, CS1, CS0 respectively. We are using Nor-flash for code storage & execution. A custom USB bootloader is stored in internal flash & execution jumps from internal to external flash.

SRAM is used mainly for LCD buffers & LCD has dedicated DMA  which reads bmps from SRAM & load into LCD display. The problem is that when I initialize SRAM according to its wait states given in the data sheet, the actual wait states I get is double of what I set. I did not understand this. Due to this it is slow and also affect the code execution.

Anyone aware of this problem. Please help.

Regards

Chaitanya.

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7 Replies
PradiptaB_11
Moderator
Moderator

Hi,

We are not aware of any such issues with the SRAM.

Can you provide a little more details on this ? How have you initialized the SRAM ?

In what time are you reading the data ?

Have you taken the setup time and hold time into consideration for all the devices that are interacting with the SRAM ?

Are you always reading the correct data or incorrect data ?

Thanks,

Pradipta.

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chku_3524716
New Contributor

Hi Pradipta,

In my project I use LPCOpen library & initialization is as follows:

STATIC const IP_EMC_STATIC_CONFIG_T SRAM_config = {

1,                                       //CS1

EMC_STATIC_CONFIG_MEM_WIDTH_16 |         //16 bit width

EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |    //CS active low

EMC_STATIC_CONFIG_BLS_HIGH,              

EMC_NANOSECOND(0),                       /*!< Write Enable Wait */

EMC_NANOSECOND(22),                      /*!< Output Enable Wait */

EMC_NANOSECOND(45),                      /*!< Read Wait */                        

EMC_NANOSECOND(45),                      /*!< Page Access Wait */

EMC_NANOSECOND(35),                      /*!< Write Wait */

EMC_CLOCK(4)                             /*!< Turn around Wait */

};

Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *)&SRAM_config);     //Sets the register values according to structure initialized

Now when I observed the waveform on oscilloscope I saw that CE pulse width came out to be near 90ns during read cycles. In datasheet width of CE is Trc(read cycle time = 45ns). Although for Nor-flash I use the same function & it came to be 75ns(when I set read wait of 70ns).

For testing I was reading a same address continuously in an infinite loop.

Yes I almost always read correct data.

Thanks,

Chaitanya.

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PradiptaB_11
Moderator
Moderator

Hi,

Can you once check the Turn around wait time you have chosen. Can you tell us how you are using EMC_Clock (4). Where do you get 4 as a value. Generally turn around time is used to deal with the bus contention issues when a read is followed by write or vice versa. SRAMs do not need this time as there will be no bus contention issues from the SRAM side as this is taken care by the OE and WE pin.

Thanks and Regards,

Pradipta.

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chku_3524716
New Contributor

Hi,

We have checked the turn around wait & it shouldn't be set to 4(= 66.66ns, since EMC clock is 60 MHz). But we also checked keeping it as 0 & still getting the same results. This could be because we are not writing anything in SRAM, continuously reading bmps from it & displaying on LCD.

Can you verify that the remaining wait states are correct. Meanwhile I will try to test the consecutive read-write code on my board.

It would be helpful if you can show me an initialization of this particular SRAM.

Thank you

Chaitanya.

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PradiptaB_11
Moderator
Moderator

Hi Chaitanya,

Can you share the function definitions for EMC_Nanosecond and EMC_Clock.

Thanks and Regards,

Pradipta.

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chku_3524716
New Contributor

Hi Pradipta,

They are macros which shifts the value left by 8 times(*256). This is then again shifted back after calculations with respect to EMC clock, so as to get a exact number to initialize the registers with.

Macros are:

#define Q24_8_FP(x)                     ((x) * 256)

#define EMC_NANOSECOND(x)               Q24_8_FP(x)

#define EMC_CLOCK(x)                    Q24_8_FP(-(x))

And the init function which convert these parameters is as follows where EMC_clock = 60000000(60MHz) & adjust simplifies the value.

STATIC uint32_t convertTimmingParam(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust)

{

    uint32_t temp;

    if (input_ns < 0) {

        return (-input_ns) >> 8;

    }

    temp = EMC_Clock / 1000000;        /* MHz calculation */

    temp = temp * input_ns / 1000;

    /* round up */

    temp += 0xFF;

    /* convert to simple integer number format */

    temp >>= 8;

    if (temp > adjust) {

        return temp - adjust;

    }

    return 0;

}

void initStaticRam(LPC_EMC_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock)

{

    LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5));

    EMC_Reg_add->STATICCONFIG0      = Static_Config->Config;

    EMC_Reg_add->STATICWAITWEN0     = convertTimmingParam(EMC_Clock, Static_Config->WaitWen, 0);

    EMC_Reg_add->STATICWAITOEN0     = convertTimmingParam(EMC_Clock, Static_Config->WaitOen, 0);

    EMC_Reg_add->STATICWAITRD0      = convertTimmingParam(EMC_Clock, Static_Config->WaitRd, 0);

    EMC_Reg_add->STATICWAITPAG0     = convertTimmingParam(EMC_Clock, Static_Config->WaitPage, 0);

    EMC_Reg_add->STATICWAITWR0      = convertTimmingParam(EMC_Clock, Static_Config->WaitWr, 0);

    EMC_Reg_add->STATICWAITTURN0    = convertTimmingParam(EMC_Clock, Static_Config->WaitTurn, 0);

}

Regards

Chaitanya.

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PradiptaB_11
Moderator
Moderator

Hi Chaitanya,

To verify as to how you are getting 90 ns as read time can you also provide the read function also. It will allow us to understand better.

Thanks,

Pradipta.

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